Publications associées à Bit slicing

Full key recovery side-channel attack against ephemeral SIKE on the Cortex-M4

Aymeric Genet, Natacha Yolande Emmanuel Marie Linard de Guertechin, Novak Kaluderovic

This paper describes the first practical single-trace side-channel power analysis of SIKE. While SIKE is a post-quantum key exchange, the scheme still relies on a secret elliptic curve scalar multiplication which involves a loop of a double-and-add procedu ...

2021

Six shades lighter: a bit-serial implementation of the AES family

Subhadeep Banik, Muhammed Fatih Balli, Sergio Roldán Lombardía

Recently, cryptographic literature has seen new block cipher designs such as PRESENT, GIFT or SKINNY that aim to be more lightweight than the current standard, i.e., AES. Even though AES family of block ciphers were designed two decades ago, they still rem ...

2021

The Area-Latency Symbiosis: Towards Improved Serial Encryption Circuits

Subhadeep Banik, Muhammed Fatih Balli, Andrea Felice Caforio

The bit-sliding paper of Jean et al. (CHES 2017) showed that the smallest-size circuit for SPN based block ciphers such as AES, SKINNY and PRESENT can be achieved via bit-serial implementations. Their technique decreases the bit size of the datapath and na ...

2020

Enhanced-performance integrated Resonant Switched-Capacitor and Buck DC-DC converters for application in extreme radiation and magnetic field environments

Giacomo Ripamonti

DC-DC converters based on Application Specific Integrated Circuits (ASICs) have been developed in this doctoral work for the High-Luminosity Large Hadron Collider (HL-LHC) experiments at CERN. They step down the voltage from a 2.5 V line and supply a load ...

EPFL2020

A Dual-Edge Pulsewidth Modulator for Fast Dynamic Response DC-DC Converters

Maher Kayal, Adil Koukab, Giacomo Ripamonti, Stefano Michelis, Federico Faccio

Voltage regulator modules are dc-dc converters that power modern microprocessors. They must exhibit a fast dynamic response, in order to achieve satisfactory regulation performance in spite of the rapid load current variations. The pulsewidth modulator is ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor

Mihai Adrian Ionescu, Anna Krammer, Teodor Rosca, Josef Andreas Schuler, Cem Alper, Wolfgang Amadeus Vitale, Arnab Biswas, Emanuele Andrea Casu, Qun Zhao

Steep-slope transistors allow to scale down the supply voltage and the energy per computed bit of information as compared to conventional field-effect transistors (FETs), due to their sub-60 mV/decade subthreshold swing at room temperature. Currently pursu ...

Nature Research2017

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Adam Shmuel Teman, Thomas Christoph Müller, Andrea Bonetti, Jeremy Hugues-Felix Constantin, Lorenz Flavio Schmid

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

Real-Time Neural Signals Decoding onto Off-the-Shelf DSP Processors for Neuroprosthetic Applications

Silvestro Micera, Stanisa Raspopovic

The control of upper limb neuroprostheses through the peripheral nervous system (PNS) can allow restoring motor functions in amputees. At present, the important aspect of the realtime implementation of neural decoding algorithms on embedded systems has bee ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Optimization of the Data Rate of an OOK CMOS Medical Transmitter Based on LC Oscillators

Catherine Dehollain, Kerim Türe, Gürkan Yilmaz, Franco Maloberti

This paper presents techniques for increasing communication data rates for OOK modulated signals in the case the carrier frequency is generated by a cross-coupled pair LC oscillator. The proposed circuitry completely turns off the transmitter during the tr ...

Ieee2016

The EPFL Combinational Benchmark Suite

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

In this paper, we present the EPFL combinational benchmark suite. We aim at completing existing benchmark suites by focusing only on natively combinational benchmarks. The EPFL combinational benchmark suite consists of 23 combinational circuits desi ...

2015

Magnetic memory devices and systems

A method of storing one or more bits of information comprising: forming a magnetic bubble; and storing a said bit of information encoded in a typology of a domain wall of said magnetic bubble. Preferably a bit is encoded using a symmetric topological state ...

2014

Two-Phase Flow Control of Electronics Cooling With Pseudo-CPUs in Parallel Flow Circuits: Dynamic Modeling and Experimental Evaluation

John Richard Thome, Jackson Braz Marcinichen, Nicolas Lamaison

On-chip two-phase cooling of parallel pseudo-CPUs integrated into a liquid pumped cooling cycle is modeled and experimentally verified versus a prototype test loop. The system's dynamic operation is studied since the heat dissipated by microprocessors is c ...

American Society of Mechanical Engineers2013

Low-Latency Elliptic Curve Scalar Multiplication

Joppe Willem Bos

This paper presents a low-latency algorithm designed for parallel computer architectures to compute the scalar multiplication of elliptic curve points based on approaches from cryptographic side-channel analysis. A graphics processing unit implementation u ...

Springer Verlag2012

Faster Software Cryptography

Dag Arne Osvik

This thesis presents work on the efficiency and security of cryptographic software. First it describes several efforts to construct very efficient implementations of cryptographic primitives. These include the Advanced Encryption Standard (AES) as well as ...

EPFL2012

ECC2K-130 on Cell CPUs

Joppe Willem Bos, Thorsten Kleinjung

This paper describes an implementation of Pollard's rho algorithm to compute the elliptic curve discrete logarithm for the Synergistic Processor Elements of the Cell Broadband Engine Architecture. Our implementation targets the elliptic curve discrete loga ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

Batch processing for efficient base-band operations in real-time GNSS software receivers

Pierre-André Farine, Cyril Botteron, Marcel Baracchi Frei

Personal Digital Assistants (PDAs) or mobile phones applications are not anymore restricted to multimedia or wireless communications, but have been extended to handle Global Navigation Satellite System (GNSS) functionalities. The new generation of portable ...

Inst Navigation, 815 15Th Th St Nw, Ste 832, Washington, Dc 20005 Usa2010

Experimental Study and Numerical Simulation of the Flindt Draft Tube Rotating Vortex

François Avellan, Monica Iliescu

The dynamics of the rotating vortex taking place in the discharge ring of a Francis turbine for partial flow rate operating conditions and cavitation free conditions is studied by carrying out both experimental flow survey and numerical simulations. 2D las ...

2007

Experimental study on prediction model for maximum rebound ratio

Jian Zhao

The proposed prediction model for estimating the maximum rebound ratio was applied to a field explosion test, Mandai test in Singapore. The estimated possible maximum peak particle velocities(PPVs) were compared with the field records. Three of the four av ...

2007

Temperature-Aware Processor Frequency Assignment for MPSoCs Using Convex Optimization

Giovanni De Micheli, David Atienza Alonso, Srinivasan Murali

The increasing processing capability of Multi-Processor Systems-on-Chips (MPSoCs) is leading to an increase in chip power dissipation, which in turn leads to significant increase in chip temperature. An important challenge facing the MPSoC designers is to ...

2007