Seyed Armin Tajalli, Yusuf Leblebici, Zeynep Toprak Deniz, Omer Can Akgun, Thomas Liechti
This paper describes the implementation of a 12-bit 230 MS/s pipelined ADC using a conventional 1.8V, 0.18μm digital CMOS process. Two-stage folded cascode OTA topology is used for improved settling performance. Extreme low-skew (less than 3ps peak-to-peak ...
IEEE2008
