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Publications associées (30)

Wafer-scale reliable switching memory based on 2-dimensional layered organic-inorganic halide perovskite

Recently, organic-inorganic halide perovskite (OHP) has been suggested as an alternative to oxides or chalcogenides in resistive switching memory devices due to low operating voltage, high ON/OFF ratio, and flexibility. The most studied OHP is 3-dimensiona ...

Royal Soc Chemistry2017

Endurance Management for Resistive Logic-In-Memory Computing Architectures

Giovanni De Micheli, Mathias Soeken, Pierre-Emmanuel Julien Marc Gaillardon

Resistive Random Access Memory (RRAM) is a promising non-volatile memory technology which enables modern in-memory computing architectures. Although RRAMs are known to be superior to conventional memories in many aspects, they suffer from a low writ ...

Ieee2017

Near-Memory Address Translation

Babak Falsafi, Javier Picorel Obando, Dorde Jevdic

Memory and logic integration on the same chip is becoming increasingly cost effective, creating the opportunity to offload data-intensive functionality to processing units placed inside memory chips. The introduction of memory-side processing units (MPUs) ...

Ieee2017

Optimization Opportunities in RRAM-based FPGA Architectures

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon

Static Random Access Memory (SRAM)-based routing multiplexers, whatever structure is employed, share a common limitation: their area, delay and power increase linearly with the input size. This property results in most SRAM-based FPGA architectures ...

IEEE2017

An Out-of-Order Load-Store Queue for Spatial Computing

Paolo Ienne, Lana Josipovic, Philip Brisk

The efficiency of spatial computing depends on the ability to achieve maximal parallelism. This necessitates memory interfaces that can correctly handle memory accesses that arrive in arbitrary order while still respecting data dependencies and ensuring ap ...

Assoc Computing Machinery2017

Fabrication, Characterization and Integration of Resistive Random Access Memories

Jury Sandrini

The functionalities and performances of today's computing systems are increasingly dependent on the memory block. This phenomenon, also referred as the Von Neumann bottleneck, is the main motivation for the research on memory technologies. Despite CMOS tec ...

EPFL2017

A High-performance FPGA Architecture Using One-Level RRAM-based Multiplexers

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon

Resistive Random Access Memory (RRAM)-based routing multiplexers, built using a one-level structure, are significantly more delay efficient than state-of-art SRAM-based implementations thanks to their lower achievable on-state resistance. In addition, the ...

2017

Nanoionics Phenomena and Devices with Oxide Thin Films

Mahmoud Hadad

The number of studies on solid state ionic thin films (Nanoionics) has increased dramatically over last decades due to their high potential in micro and nanoscale technologies. Micro solid oxide fuel cells (micro-SOFC), and resistive switching memories (Re ...

EPFL2017

An MIG-based Compiler for Programmable Logic-in-Memory Architectures

Giovanni De Micheli, Mathias Soeken, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

Resistive memories have gained high research attention for enabling design of in-memory computing circuits and systems. We propose for the first time an automatic compilation methodology suited to a recently proposed computer architecture solely based on r ...

Ieee2016

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Oskar Andersson

In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch a ...

Institute of Electrical and Electronics Engineers2016

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