Point-contact transistor

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Publications associées (30)

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Atomically thin two-dimensional (2D) materials belonging to transition metal dichalcogenides, due to their physical and electrical properties, are an exceptional vector for the exploration of next-generation semiconductor devices. Among them, due to the po ...

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22% Efficient Dopant-free Interdigitated Back Contact Silicon Solar Cells

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AMER INST PHYSICS2018

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The growing research on two-dimensional materials reveals their exceptional physical properties and enormous potential for future applications and investigation of advanced physics phenomena. They represent the ultimate limit in terms of active channel thi ...

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Full-Area Passivating Contacts with High and Low Thermal Budgets: Solutions for High Efficiency c-Si Solar Cells

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Today more than 90% of the global PV market is covered by c-Si solar cells which are limited by recombination losses at the metal-semiconductor interface. This recombination path can be avoided by separating the metal from the c-Si wafer by introducing a b ...

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Semiconductor devices with multiple channels and three-dimensional electrodes

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The present invention relates, for example, to a semiconductor structure containing multiple parallel channels in which several parallel conductive channels are formed within the semiconductor structure. Electric contact or electrostatic control over all t ...

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Variability of Low Frequency Noise and mismatch in enclosed-gate and standard nMOSFETs

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Variability of Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) is an important concern for many analog CMOS integrated circuits. In this paper, transistors with enclosed gate layout are examined and compared with standard layout transistors, wit ...

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A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

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We present a complete pixel based on a single-photon avalanche diode (SPAD) fabricated in a backside-illuminated (BSI) 3D IC technology. The chip stack comprises an image sensing tier produced in a 65-nm image sensor technology and a data processing tier i ...

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Characterization of bipolar transistors for cryogenic temperature sensors in standard CMOS

Edoardo Charbon, Harald Arjan Robert Homulle, Fabio Sebastiano

This paper presents the cryogenic characterization of the bipolar substrate PNPs that are typically employed as sensing elements in CMOS integrated temperature sensors. PNPs realized in a standard 160-nm CMOS technology were characterized over the temperat ...

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Performance of Indium Gallium Zinc Oxide Thin-Film Transistors in Saline Solution

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Transistors are often envisioned as alternative transducing devices to microelectrodes to communicate with the nervous system. Independently of the selected technology, the transistors should have reliable performance when exposed to physiological conditio ...

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Simulation, Analysis, and Verification of Substrate Currents for Layout Optimization of Smart Power ICs

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Today circuit failures in Smart Power ICs due to substrate couplings are partially addressed during the circuit design phase. The state-of-the-art guidelines for the optimization of parasitic couplings provide mainly qualitative rules, which are difficult ...

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