Publications associées à Amplificateur de détection

Memory chip or memory array for wide-voltage range in-memory computing using bitline technology

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Marco Antonio Rios, William Andrew Simon

A random access memory having a memory array having a plurality of local memory groups, each local memory group including a plurality of bitcells arranged in a bitcell column, a pair of local bitlines operatively connected to the plurality of bitcells, a p ...

2021

Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Miguel Peon Quiros, Marco Antonio Rios

Resistive switching memory technologies (RRAM) are seen by most of the scientific community as an enabler for Edge-level applications such as embedded deep Learning, AI or signal processing of audio and video signals. However, going beyond a "simple'' repl ...

IEEE2020

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

Robert Giterman, Odem Harel

Embedded memories, mostly implemented with static random access memory (SRAM), dominate the area and power of integrated circuits. Gain-cell embedded DRAM (GC-eDRAM) is an alternative to SRAM due to its high density, low power consumption, and two-ported f ...

ELSEVIER SCI LTD2020

Design Guidelines for High-Performance SCM Hierarchies

Babak Falsafi, Edouard Bugnion, Alexandros Daglis, Javier Picorel Obando, Mark Johnathon Sutherland, Dmitrii Ustiugov, Dionysios Pnevmatikatos

With emerging storage-class memory (SCM) nearing commercialization, there is evidence that it will deliver the much-anticipated high density and access latencies within only a fewfactors of DRAM. Nevertheless, the latency-sensitive nature of memory-residen ...

ACM2018

An Accelerator for High Efficient Vision Processing

Paolo Ienne, Robert Fasthuber, Zidong Du, Qi Guo

In recent years, neural network accelerators have been shown to achieve both high energy efficiency and high performance for a broad application scope within the important category of recognition and mining applications. Still, both the energy efficiency a ...

Ieee-Inst Electrical Electronics Engineers Inc2017

Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays

Paolo Ienne, Hossein Asadi, Sadegh Yazdanshenas

Nanoelectromechanical (NEM) relays are a promising emerging technology that has gained widespread research attention due to its zero leakage current, sharp ON-OFF transitions, and complementary metal-oxide-semiconductor compatibility. As a result, NEM rela ...

Institute of Electrical and Electronics Engineers2016

Low-Voltage Read/Write Circuit Design for Transistorless ReRAM Crossbar Arrays in 180nm CMOS Technology

Davide Sacchetto, Yusuf Leblebici, Jury Sandrini, Tugba Demirci, Maxime Victor Thammasack

This paper presents a read-write design solution for passive ReRAM crossbar memory arrays to overcome the sneak current paths problem. The proposed circuitry includes an auto-calibration feature to overcome the sneak current effects during the READ operati ...

2015

ShiDianNao: shifting vision processing closer to the sensor

Paolo Ienne, Robert Fasthuber, Zidong Du

In recent years, neural network accelerators have been shown to achieve both high energy efficiency and high performance for a broad application scope within the important category of recognition and mining applications. Still, both the energy efficiency a ...

ACM2015

Design of High-Temperature SRAM for Reliable Operation Beyond 250 C

Yusuf Leblebici, Radisav Cojbasic

In this paper, we analyze the 6T SRAM cell failures caused by temperature and supply voltage variations, and we explore the design of robust SRAM cells for high temperature operation. This integral SRAM reliability study is performed using 180nm SOI CMOS p ...

2015

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

Georgios Karakonstantis

In this paper, a multi-level wordline driver scheme is presented to improve 6T-SRAM read and write stability. The proposed wordline driver generates a shaped pulse during the read mode and a boosted wordline during the write mode. During read, the shaped p ...

Elsevier2014

Dynamic stability and noise margins of SRAM arrays in nanoscaled technologies

Adam Shmuel Teman

SRAM stability is one of the primary bottlenecks of current VLSI system design, and the unequivocal supply voltage scaling limiter. Static noise margin metrics have long been the de-facto standard for measuring this stability and estimating the yield of SR ...

IEEE2014

Semiconductor memory cell, array, architecture and device, and method of operating same

Serguei Okhonin

There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of ...

2007