Publications associées à HiSilicon

On-Chip Fully Reconfigurable Artificial Neural Network in 16 nm FinFET for Positron Emission Tomography

Edoardo Charbon, Claudio Bruschini, Emanuele Ripiccini, Andrada Alexandra Muntean

Smarty is a fully-reconfigurable on-chip feed-forward artificial neural network (ANN) with ten integrated time-to-digital converters (TDCs) designed in a 16 nm FinFET CMOS technology node. The integration of TDCs together with an ANN aims to reduce system ...

Ieee-Inst Electrical Electronics Engineers Inc2024

Integrated electronics for time-of-flight positron emission tomography photodetectors

Andrada Alexandra Muntean

Positron emission tomography is a nuclear imaging technique well known for its use in oncology for cancer diagnosis and staging. A PET scanner is a complex machine which comprises photodetectors placed in a ring configuration that detect gamma photons gen ...

EPFL2023

Gem5-X : A Many-Core Heterogeneous Simulation Platform for Architectural Exploration and Optimization

David Atienza Alonso, Marina Zapater Sancho, William Andrew Simon, Yasir Mahmood Qureshi

The increasing adoption of smart systems in our daily life has led to the development of new applications with varying performance and energy constraints, and suitable computing architectures need to be developed for these new applications. In this paper, ...

2021

Exploration of Negative Capacitance Devices and Technologies

Ali Saeidi

Conventional device scaling has been the main guiding principle of the MOS device engineering over these past years. However, this aggressive scaling would be eventually limited due to the inability to remove the heat generated by MOSFET devices. The power ...

EPFL2019

Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon, Edouard Giacomin

Routing multiplexers based on pass-transistors or transmission gates are an essential components in many digital integrated circuits. However, whatever structure is employed, CMOS multiplexers have two major limitations: 1) their delay is linearly related ...

Ieee-Inst Electrical Electronics Engineers Inc2017

Total ionizing dose effects on a 28 nm Hi-K metal-gate CMOS technology up to 1 Grad

Chunmin Zhang, Alessandro Pezzotta

This paper presents the results of an irradiation study on single transistors manufactured in a 28 nm high-k commercial CMOS technology up to 1 Grad. Both nMOSFET and pMOSFET transistors have been irradiated and electrical parameters have been measured. Fo ...

2017

A Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

Giovanni De Micheli, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon, Hassan Ghasemzadeh Mohammadi

This paper deals with the effects of faults on circuits implemented with controllable-polarity transistors. We propose a new fault model that suits the characteristics of these devices, and report the results of a SPICE-based analysis of the effects of fau ...

2016

On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

Giovanni De Micheli, Eduardo Sanchez, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon, Hassan Ghasemzadeh Mohammadi

This paper first explores the effects of faults on circuits implemented with controllable-polarity transistors. We propose a new fault model that suits the characteristics of these devices, and report the results of a SPICE-based analysis of the effects of ...

IEEE2015

New Data Structures and Algorithms for Logic Synthesis and Verification

Luca Gaetano Amarù

The strong interaction between Electronic Design Automation (EDA) tools and Complementary Metal-Oxide Semiconductor (CMOS) technology contributed substantially to the advancement of modern digital electronics. The continuous downscaling of CMOS Field Effec ...

EPFL2015

Design of a parallel low power flash A/D converter for the sub-sampling IR-UWB receiver

Catherine Dehollain, Shenjie Wang

This paper presents the design of a dual-channel 4-bit analog-to-digital converter (ADC) for the sub-sampling impulse radio ultra-wideband receiver with the sampling rate of 2.112 GS/s. The ADC's specifications are optimized at the system level. Two parall ...

Springer Verlag2013

Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Pascal Andreas Meinerzhagen

Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage (VDD) to minimize both dynamic and static power consumption. Embedded memories can easily dominate the overall sili ...

2013

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors

Giovanni De Micheli, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

This brief presents a novel power-gating technique for differential cascade voltage switch logic (DCVSL) based on double-gate (DG) controllable-polarity field-effect transistors (FETs). DG controllable-polarity FETs, commonly referred to as ambipolar trans ...

Ieee-Inst Electrical Electronics Engineers Inc2013

Physics-based compact model for ultra-scaled FinFETs

Jean-Michel Sallese, Ashkhen Yesayan, Christophe Lallement

A physical and explicit compact model for lightly doped FinFETs is presented. This design-oriented model is valid for a large range of silicon Fin widths and lengths, using only a very few number of model parameters. The quantum mechanical effects (QMEs), ...

2011

Self-Assembled Liquid-Gated Zinc Oxide Nanowire Transistors : Fabrication and Sensing Operation

Vivek Pachauri

This thesis aims at the site-specific realization of self-assembled field-effect transistors (FETs) based on semiconducting Zinc oxide NWs and their application towards chemical and bio-sensing in liquid medium. At first, a solution based growth method for ...

EPFL2011

Inducing Thermal-Awareness in Multicore Systems Using Networks-on-Chip

David Atienza Alonso

Technology scaling imposes an ever increasing temperature stress on digital circuit design due to transistor density, especially on highly integrated systems, such as Multi- Processor Systems-on-Chip (MPSoCs). Therefore, temperature-aware design is mandato ...

IEEE Computer Society2009

Network-On-Chip Design and Synthesis Outlook

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini

With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor Systems-On-Chip (MPSoCs) consisting of complex integrated components communicating with each other at very high-speed rates. Intercommunication ...

2008

Fabrication of silicon nano wires and gate-all-around MOS devices

Didier Bouvet, Kirsten Emilie Moselund

The invention relates to methods for manufacturing semiconductor devices. Processes are disclosed for implementing suspended single crystal silicon nano wires (NWs) using a combination of anisotropic and isotropic etches and spacer creation for sidewall pr ...

2007