Instruction set architecture

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Publications associées (26)

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Emerging technologies such as plasmonics and photonics are promising alternatives to CMOS for high throughput applications, thanks to their waveguide's low power consumption and high speed of computation. Besides these qualities, these novel technologies a ...

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SpecROP: Speculative Exploitation of ROP Chains

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Speculative execution attacks, such as Spectre, reuse code from the victim’s binary to access and leak secret information during speculative execution. Every variant of the attack requires very particular code sequences, necessitating elaborate gadget-sear ...

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Boolean satisfiability in quantum compilation

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Quantum compilation is the task of translating a quantum algorithm implemented in a high-level quantum programming language into a technology-dependent instructions flow for a physical quantum computer. To tackle the large gap between the quantum program a ...

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Modifying Stride Length in Isolation and in Combination With Foot Progression Angle and Step Width Can Improve Knee Kinetics Related to Osteoarthritis; A Preliminary Study in Healthy Subjects

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The purpose of this study was to determine the effects of modifying stride length (SL) on knee adduction and flexion moments, two markers of knee loading associated with medial-compartment knee osteoarthritis (OA) progression. This study also tested if SL ...

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Program compilation for large-scale quantum computers

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Practical realizations of quantum computers are poised to deliver outstanding computational capabilities far beyond the reach of any classical supercomputer. While classical systems are reliably implemented using CMOS technology, the fabrication of quantu ...

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Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

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Modern GPUs suffer from cache contention due to the limited cache size that is shared across tens of concurrently running warps. To increase the per-warp cache size prior techniques proposed warp throttling which limits the number of active warps. Warp thr ...

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