Publications associées à Instruction cycle

Green Cryptography and Other Optimisations

The spectral decomposition of cryptography into its life-giving components yields an interlaced network of tangential and orthogonal disciplines that are nonetheless invariably grounded by the same denominator: their implementation on commodity computing p ...

EPFL2023

Imprecise Store Exceptions

Babak Falsafi, Mathias Josef Payer, Yuanlong Li, Siddharth Gupta, Yunho Oh, Qingxuan Kang, Abhishek Bhattacharjee

Precise exceptions are a cornerstone of modern computing as they provide the abstraction of sequential instruction execution to programmers while accommodating microarchitectural optimizations. However, increasing compute capabilities in deep memory hierar ...

ACM2023

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Mathias Josef Payer, Mirjana Stojilovic, Shashwat Shrivastava, Ognjen Glamocanin, Jinwei Yao, Nour Ardo

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

2023

Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era

Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud

Given the need for efficient high-performance computing, computer architectures combining CPUs, GPUs, and FPGAs are nowadays prevalent. However, each of these components suffers from electrical-level security risks. Moving to heterogeneous systems, with th ...

2022

Do Children Adapt Their Perspective to a Robot When They Fail to Complete a Task?

Pierre Dillenbourg, Elmira Yadollahi, Ana Paiva

Spatial understanding and communication are essential skills in human interaction. An adequate understanding of others' spatial perspectives can increase the quality of the interaction, both perceptually and cognitively. In this paper, we take the first st ...

Assoc Computing Machinery2022

Micro-architectural analysis of in-memory OLTP: Revisited

Anastasia Ailamaki, Danica Porobic, Utku Sirin

Micro-architectural behavior of traditional disk-based online transaction processing (OLTP) systems has been investigated extensively over the past couple of decades. Results show that traditional OLTP systems mostly under-utilize the available micro-archi ...

2021

On Block Prediction For Learning-Based Point Cloud Compression

Touradj Ebrahimi, Davi Nachtigall Lazzarotto, Evangelos Alexiou

Point clouds are among popular visual representations for immersive media. However, the vast amount of information generated during their acquisition requires effective compression for practical applications. Although relevant activities from standardizati ...

IEEE2021

Micro-architectural Analysis of OLAP: Limitations and Opportunities

Anastasia Ailamaki, Utku Sirin

Understanding micro-architectural behavior is important for efficiently using hardware resources. Recent work has shown that in-memory online transaction processing (OLTP) systems severely underutilize their core micro-architecture resources [29]. Whereas, ...

ASSOC COMPUTING MACHINERY2020

Distributed Logless Atomic Durability with Persistent Memory

Babak Falsafi, Alexandros Daglis, Siddharth Gupta

Datacenter operators have started deploying Persistent Memory (PM), leveraging its combination of fast access and persistence for significant performance gains. A key challenge for PM-aware software is to maintain high performance while achieving atomic du ...

2019

Improving Main-memory Database System Performance through Cooperative Multitasking

Georgios Psaropoulos

Database systems access memory either sequentially or randomly. Contrary to sequential access and despite the extensive efforts of computer architects, compiler writers, and system builders, random access to data larger than the processor cache has been s ...

EPFL2019

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories

David Atienza Alonso, Marina Zapater Sancho, Pierre-Emmanuel Julien Marc Gaillardon, Yasir Mahmood Qureshi, Xifan Tang, Edouard Giacomin, João Miguel Morgado Pereira Vieira

The need for running complex Machine Learning (ML) algorithms, such as Convolutional Neural Networks (CNNs), in edge devices, which are highly constrained in terms of computing power and energy, makes it important to execute such applications efficiently. ...

2019

Near-Optimal Noisy Group Testing via Separate Decoding of Items

Volkan Cevher, Jonathan Mark Scarlett

In this paper, we revisit an efficient algorithm for noisy group testing in which each item is decoded separately (Malyutov and Mateev, 1980), and develop novel performance guarantees via an information-theoretic framework for general noise models. For the ...

IEEE2018

Automated Synthesis of Adversarial Workloads for Network Functions

Rishabh Ramesh Iyer, Aikaterini Argyraki, Arseniy Zaostrovnykh, Jonas Fietz, Luis David Figueiredo Mascarenhas Moreira Pedrosa

Software network functions promise to simplify the deployment of network services and reduce network operation cost. However, they face the challenge of unpredictable performance. Given this performance variability, it is imperative that during deployment, ...

ACM2018

Near-Optimal Noisy Group Testing via Separate Decoding of Items

Volkan Cevher, Jonathan Mark Scarlett

The group testing problem consists of determining a small set of defective items from a larger set of items based on a number of tests, and is relevant in applications such as medical testing, communication protocols, pattern matching, and more. In this pa ...

2018

Unified prefetching into instruction cache and branch target buffer

Babak Falsafi, Boris Robert Grot, Ilknur Cansu Kaynak

A system and method of coupling a Branch Target Buffer (BTB) content of a BTB with an instruction cache content of an instruction cache. The method includes: tagging a plurality of target buffer entries that belong to branches within a same instruction blo ...

2017

The EPFL Combinational Benchmark Suite

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

In this paper, we present the EPFL combinational benchmark suite. We aim at completing existing benchmark suites by focusing only on natively combinational benchmarks. The EPFL combinational benchmark suite consists of 23 combinational circuits desi ...

2015

Memory Systems and Interconnects for Scale-Out Servers

Stavros Volos

The information revolution of the last decade has been fueled by the digitization of almost all human activities through a wide range of Internet services. The backbone of this information age are scale-out datacenters that need to collect, store, and proc ...

EPFL2015

ADDICT: Advanced Instruction Chasing for Transactions

Anastasia Ailamaki, Pinar Tözün

Recent studies highlight that traditional transaction processing systems utilize the micro-architectural features of modern processors very poorly. L1 instruction cache and long-latency data misses dominate execution time. As a result, more than half of th ...

2014

A paradox of eventual linearizability in shared memory

Rachid Guerraoui, Eric Ruppert

This paper compares, for the rst time, the computational power of linearizable objects with that of eventually linearizable ones. We present the following paradox. We show that, unsurprisingly, no set of eventually linearizable objects can (1) implement an ...

ACM Press2014

STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution

Anastasia Ailamaki, Pinar Tözün, Xin Tong

Online transaction processing (OLTP) workload performance suffers from instruction stalls; the instruction footprint of a typical transaction exceeds by far the capacity of an L1 cache, leading to ongoing cache thrashing. Several proposed techniques remove ...

2013