Publications associées à Verilog

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

EdgeAI-Aware Design of In-Memory Computing Architectures

Marco Antonio Rios

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

EPFL2024

A 3.3-Gb/s SPAD-Based Quantum Random Number Generator

Edoardo Charbon, Pouyan Keshavarzian, Francesco Gramuglia, Mario Stipcevic

Quantum random number generators (QRNGs) are a burgeoning technology used for a variety of applications, including modern security and encryption systems. Typical methods exploit an entropy source combined with an extraction or bit generation circuit in or ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2023

Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level Synthesis

Francesco Regazzoni, Andrea Guerrieri, Andres Upegui

High-level synthesis is a mature Electronics Design Automation (EDA) technology for building hardware design in a short time. It produces automatically HDL code for FPGAs out of C/C++, bridging the gap from algorithm to hardware. Nevertheless, sometimes th ...

IEEE2022

Analytic modelling of passive microfluidic mixers

Jean-Michel Sallese, Christophe Lallement

This paper deals with a new analytical model for microfluidic passive mixers. Two common approaches already exist for such a purpose. On the one hand, the resolution of the advection-diffusion-reaction equation (ADRE) is the first one and the closest to ph ...

AMER INST MATHEMATICAL SCIENCES-AIMS2022

FPGA-to-CPU Undervolting Attacks

Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud

FPGAs are proving useful and attractive for many applications, thanks to their hardware reconfigurability, low power, and high-degree of parallelism. As a result, modern embedded systems are often based on systems-on-chip (SoCs), where CPUs and FPGAs share ...

IEEE2022

High-Level Synthesis of Dynamically Scheduled Circuits

Lana Josipovic

High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. These tools almost universally build datapaths that are controlled using a centralized controller which relies on a static, compile-time schedule to determine ...

EPFL2021

Further Results on Efficient Implementations of Block Cipher Linear Layers

Subhadeep Banik

At the FSE conference of ToSC 2018, Kranz et al. presented their results on shortest linear programs for the linear layers of several well known block ciphers in literature. Shortest linear programs are essentially the minimum number of 2-input xor gates r ...

2021

Programming Heterogeneous CPU-GPU Systems by High-Level Dataflow Synthesis

Marco Mattavelli, Endri Bezati, Aurélien François Gilbert Bloch

Heterogeneous processing platforms combining in various architectures CPUs, GPUs, and programmable logic, are continuously evolving providing at each generation higher theoretical levels of computing performance. However, the challenge of how efficiently s ...

IEEE2020

Buffer Placement and Sizing for High-Performance Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Shabnam Sheikhha

Commercial high-level synthesis tools typically produce statically scheduled circuits. Yet, effective C-to-circuit conversion of arbitrary software applications calls for dataflow circuits, as they can handle efficiently variable latencies (e.g., caches) a ...

ASSOC COMPUTING MACHINERY2020

More Results on Shortest Linear Programs

Subhadeep Banik

At the FSE conference of ToSC 2018, Kranz et al. presented their results on shortest linear programs for the linear layers of several well known block ciphers in literature. Shortest linear programs are essentially the minimum number of 2-input xor gates r ...

2019

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Giovanni De Micheli, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon, Edouard Giacomin

In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can ...

2018

System Level simulation framework for the ASICs development of a novel particle physics detector

Yusuf Leblebici, Alessandro Caratelli, Davide Ceresa, Simone Scarfì

The simulation of the passage of particles through matter using Monte Carlo methods is broadly used in the development of particle detectors for high energy physics experiments. To develop the readout electronics for the Compact Muon Solenoid (CMS) experim ...

IEEE2018

Code Generation in Computational Neuroscience: A Review of Tools and Techniques

Michael Lee Hines, Pramod Shivaji Kumbhar, Romain Brette

Advances in experimental techniques and computational power allowing researchers to gather anatomical and electrophysiological data at unprecedented levels of detail have fostered the development of increasingly complex models in computational neuroscience ...

2018

Circuit Design, Architecture and CAD for RRAM-based FPGAs

Xifan Tang

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two ...

EPFL2017

Hierarchical Reversible Logic Synthesis Using LUTs

Giovanni De Micheli, Mathias Soeken

Today's rapid advances in the physical implementation of quantum computers demand for scalable synthesis methods in order to map practical logic designs to quantum architectures. We present a synthesis algorithm for quantum computing based on k-LUT network ...

IEEE2017

Virtual Prototyping Methodology for Power Automation Cyber-Physical-Systems

Juan Sebastian Rodriguez Estupinan

In this thesis, the author proposes a circular system development model which considers all the stages in a typical development process for industrial systems. In particular, the present work shows that the use of virtual prototyping at early stages of the ...

EPFL2017

Single-End FPGA-Based Fault Location System for Radial/Meshed AC/DC Networks based on the Electromagnetic Time Reversal Theory

Mario Paolone, Farhad Rachidi-Haeri, Reza Razzaghi

The paper presents an automated single-end FPGA-based fault location system for AC/DC power networks. The proposed system is based on the electromagnetic time reversal theory and uses an automated FPGA-based real-time simulator to perform the fault locatio ...

IEEE2017

An automated FPGA real-time simulator for power electronics and power systems electromagnetic transient applications

Mario Paolone, Farhad Rachidi-Haeri, Reza Razzaghi

The paper presents an automated FPGA-based real-time electromagnetic transients simulator for power electronics and power systems applications. The simulator features an automated procedure enabling its straightforward applications to different topologies ...

Elsevier2016

Automatic generation of program execution that reaches a given failure point

George Candea, Cristian Zamfir

An execution of a target software program that causes a particular bug to manifest itself is generated. A target software program is received. A bug report generated by an execution of the target software program is received. The bug report describes a par ...

2015