Publications associées à Langage Ladder

Homogenous power distribution along gyrotron collector walls

Stefano Alberti, Jean-Philippe Hogge, Damien Fasel, Ugo Siravo, Jérémie Dubray, Miguel Filipe Silva Füglister, Pierre-François Isoz

EC RF power sources will play a major role in the future operation of large scale tokamaks (ITER, DEMO). A 1MW/170GHz gyrotron is the standard RF power unit considered for ITER. Even though the efficiency of such devices has been significantly increased th ...

2023

Dynamic Probabilistic Pruning: A General Framework for Hardware-Constrained Pruning at Different Granularities

Alexandre Schmid, Lizeth Gonzalez Carabarin

Unstructured neural network pruning algorithms have achieved impressive compression ratios. However, the resulting-typically irregular-sparse matrices hamper efficient hardware implementations, leading to additional memory usage and complex control logic t ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Exploring negative capacitance and neuromorphic devices based on CMOS-compatible ferroelectric HfO2

Carlotta Gastaldi

Ferroelectric materials are explored for numerous applications thanks to their properties associated with electrically switchable spontaneous polarization. Perovskites are an established class of ferroelectrics used for sensors and actuators. However, they ...

EPFL2022

Logic-in-memory based on an atomically thin semiconductor

Aleksandra Radenovic, Andras Kis, Mukesh Kumar Tripathi, Ahmet Avsar, Yanfei Zhao, Guilherme Migliato Marega, Zhenyu Wang

The growing importance of applications based on machine learning is driving the need to develop dedicated, energy-efficient electronic hardware. Compared with von Neumann architectures, which have separate processing and storage units, brain-inspired in-me ...

2020

A Compiler for Parallel and Resource-Constrained Programmable in-Memory Computing

Giovanni De Micheli, Mathias Soeken, Pierre-Emmanuel Julien Marc Gaillardon, Giulia Meuli

Solid-state resistive switches have recently enabled low-power, scalable, non-volatile memories. Their proven intrinsic logic operation, allowing design of in-memory computing systems, attracted the attention of the research community. A Programmable Logic ...

2017

Endurance Management for Resistive Logic-In-Memory Computing Architectures

Giovanni De Micheli, Mathias Soeken, Pierre-Emmanuel Julien Marc Gaillardon

Resistive Random Access Memory (RRAM) is a promising non-volatile memory technology which enables modern in-memory computing architectures. Although RRAMs are known to be superior to conventional memories in many aspects, they suffer from a low writ ...

Ieee2017

Configuration logics: Modeling architecture styles

Joseph Sifakis, Simon Bliudze, Anastasia Mavridou, Eduard Baranov

We study a framework for the specification of architecture styles as families of architectures involving a common set of types of components and coordination mechanisms. The framework combines two logics: 1) interaction logics for the specification of arch ...

Elsevier Science Inc2017

A PLiM Computer for the Internet of Things

Giovanni De Micheli, Mathias Soeken, Pierre-Emmanuel Julien Marc Gaillardon

Emerging applications are dramatically changing computer architecture requirements, with a shift toward big data that is processed using simple computations. A programmable logic-in-memory (PLiM) computer can allow memory cells to perform primitive logic o ...

2017

Robust Hierarchically Structured Biphasic Ambipolar Oxide Photoelectrodes for Light-Driven Chemical Regulation and Switchable Logic Applications

Kevin Sivula, Florian Le Formal, Nestor Guijarro Carratala, Xavier Adrian Jeanbourquin, Mathieu Steven Prévot, Wiktor Stefan Bourée

Tunable ambipolar photoelectrochemical behavior emerges from microdomains of nanostructured p-type CuFeO2 and n-type Fe2O3 that arise from a single facile solution-processed thin fi lm. The switchable operation of this system is controlled by chemical, opt ...

Wiley-Blackwell2016

The Programmable Logic-in-Memory (PLiM) Computer (Invited)

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Anupam Chattopadhyay

Realization of logic and storage operations in memristive circuits have opened up a promising research direction of in-memory computing. Elementary digital circuits, e.g., Boolean arithmetic circuits, can be economically realized within memristive circuits ...

Ieee2016

Subdomain and Access Pattern Privacy Trading off Confidentiality and Performance

Bin Lu, Thomas Locher, Matus Harvan

Homomorphic encryption and secure multi-party computation enable computations on encrypted data. However, both techniques suffer from a large performance overhead. While advances in algorithms might reduce the overhead, we show that achieving perfect (or e ...

Scitepress2016

High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms

Marco Mattavelli, Endri Bezati, Simone Casale Brunet

The growing complexity of digital signal processing applications make a compelling case the use of high-level design and synthesis methodologies for the implementation on programmable logic devices and embedded processors. Past research has shown that, for ...

2016

Applying model checking to industrial-sized PLC programs

Simon Bliudze, Jean-Charles Tournier, Borja Fernandez Adiego

Programmable Logic Controllers (PLCs) are embedded computers widely used in industrial control systems. Ensuring that a PLC software complies with its specification is a challenging task. Formal verification has become a recommended practice to ensure the ...

Institute of Electrical and Electronics Engineers2015

Multiple Independent Gate FETs: How Many Gates Do We Need?

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Subhasish Mitra, Luca Gaetano Amarù

Multiple Independent Gate Field Effect Transistors (MIGFETs) are expected to push FET technology further into the semiconductor roadmap. In a MIGFET, supplementary gates either provide (i) enhanced conduction properties or (ii) more intelligent sw ...

IEEE2015

Configuration Logics: Modelling Architecture Styles

Joseph Sifakis, Simon Bliudze, Anastasia Mavridou, Eduard Baranov

We study a framework for the specification of architecture styles as families of architectures involving a common set of types of components and coordination mechanisms. The framework combines two logics: 1) interaction logics for the specification of arch ...

Springer Int Publishing Ag2015

A New Basic Logic Structure for Data-Path Computation

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

Nowadays, Field Programmable Gate Arrays (FPGA) implement arithmetic functions using specific circuits at the logic block level, such as the carry paths, or at the structure level adopting Digital Signal Processing (DSP) blocks. Nevertheless, all these app ...

2014

Coarse Grain Clock Gating Of Streaming Applications In Programmable Logic Implementations

Marco Mattavelli, Endri Bezati, Simone Casale Brunet

Streaming applications describe a broad class of computing algorithms in areas such as signal processing, media coding and compression, cryptography, video analytics, network touting and packet processing and many others. For many of these applications, pr ...

Ieee2014

Non-LUT field-programmable gate arrays

Paolo Ienne, Grace Zgheib, David Novo Bruna, Hadi Parandeh Afshar

New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels ...

2014

Model-based automated testing of critical PLC programs

Simon Bliudze, Jean-Charles Tournier

Testing of critical PLC (Programmable Logic Controller) programs remains a challenging task for control system engineers as it can rarely be automated. This paper proposes a model-based approach which uses the BIP (Behavior, Interactions and Priorities) fr ...

IEEE2013

A Case for Heterogeneous Technology-Mapping: Soft versus Hard Multiplexers

Paolo Ienne, Madhura Purnaprajna

Lookup table-based FPGAs offer flexibility but compromise on performance, as compared to custom CMOS implementations. This paper explores the idea of minimising this performance gap by using fixed, fine-grained, non-programmable logic structures in place o ...

Ieee2013