Publications associées à Celeron

Nonlinear Inverse Problems in Quantitative Phase Imaging

The topic of this thesis is the development of new algorithmic reconstruction methods for quantitative phase imaging (QPI). In the past decade, advanced QPI has emerged as a valuable tool to study label-free biological samples and uncover their 3D structur ...

EPFL2022

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

Paolo Ienne, Mikhail Asiatici

Applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on FPGAs due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by re ...

ASSOC COMPUTING MACHINERY2022

Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs

Paolo Ienne, Mikhail Asiatici

FPGAs rely on massive datapath parallelism to accelerate applications even with a low clock frequency. However, applications such as sparse linear algebra and graph analytics have their throughput limited by irregular accesses to external memory for which ...

ASSOC COMPUTING MACHINERY2019

End-to-End Industrial Study of Retiming

Giovanni De Micheli, Cunxi Yu, Maciej Jerzy Ciesielski

Sequential circuits are combinational circuits that are separated by registers. Retiming is considered as the most promising technique for optimizing sequential circuits, that involves moving the edge-triggered registers across the combinational logic with ...

IEEE2018

A portable platform for accelerated PIC codes and its application to GPUs using OpenACC

Laurent Villard, Stephan Brunner, Emmanuel Lanti, Trach-Minh Tran, Claudio Gheller

We present a portable platform, called PIC_ENGINE, for accelerating Particle-In-Cell (PIC) codes on heterogeneous many-core architectures such as Graphic Processing Units (GPUs). The aim of this development is efficient simulations on future exascale syste ...

Elsevier Science Bv2016

Caching Gaussians: Minimizing Total Correlation on the Gray–Wyner Network

Michael Christoph Gastpar, Guillaume Jean Op 't Veld

We study a caching problem that resembles a lossy Gray–Wyner network: A source produces vector samples from a Gaussian distribution, but the user is interested in the samples of only one component. The encoder first sends a cache message without any knowle ...

Ieee2016

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Oskar Andersson

In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch a ...

Institute of Electrical and Electronics Engineers2016

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay

Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist th ...

2015

High Frequency Instrument data processing

Julien Lesgourgues, Xin Chen, Fabio Finelli

We describe the processing of the 531 billion raw data samples from the High Frequency Instrument (HFI), which we performed to produce six temperature maps from the first 473 days of Planck-HFI survey data. These maps provide an accurate rendition of the s ...

Edp Sciences S A2014

14XX nm-wavelength electrically-pumped VECSELs fabricated by wafer fusion

Elyahou Kapon, Alexandru Mereuta, Vladimir Iakovlev, Alexei Sirbu, Andrei Caliman, Kamil Pawel Pierscinski

We report on the design, fabrication and characterization of electrically pumped vertical external cavity surface emitting lasers (EP-VECSELs) emitting at 1470 nm. We demonstrate 6.2 mW of CW output power, which represents the highest power value reported ...

Optical Society of America2013

Two-Phase Flow Control of Electronics Cooling With Pseudo-CPUs in Parallel Flow Circuits: Dynamic Modeling and Experimental Evaluation

John Richard Thome, Jackson Braz Marcinichen, Nicolas Lamaison

On-chip two-phase cooling of parallel pseudo-CPUs integrated into a liquid pumped cooling cycle is modeled and experimentally verified versus a prototype test loop. The system's dynamic operation is studied since the heat dissipated by microprocessors is c ...

American Society of Mechanical Engineers2013

Scale-Out Processors

Pejman Lotfi Kamran

Global-scale online services, such as Google’s Web search and Facebook’s social networking, run in large-scale datacenters. Due to their massive scale, these services are designed to scale out (or distribute) their respective loads and datasets across thou ...

EPFL2013

STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution

Anastasia Ailamaki, Pinar Tözün, Xin Tong

Online transaction processing (OLTP) workload performance suffers from instruction stalls; the instruction footprint of a typical transaction exceeds by far the capacity of an L1 cache, leading to ongoing cache thrashing. Several proposed techniques remove ...

2013

TamaRISC-CS: An Ultra-Low-Power Application-Specific Processor for Compressed Sensing

David Atienza Alonso, Pascal Andreas Meinerzhagen, Andreas Peter Burg, Jeremy Hugues-Felix Constantin, Ahmed Yasir Dogan, Oskar Andersson

Compressed sensing (CS) is a universal technique for the compression of sparse signals. CS has been widely used in sensing platforms where portable, autonomous devices have to operate for long periods of time with limited energy resources. Therefore, an ul ...

2012

Scale-Out Processors

Babak Falsafi, Michael Ferdman, Boris Robert Grot, Yusuf Onur Koçberber, Pejman Lotfi Kamran, Stavros Volos, Javier Picorel Obando, Al Mutaz Adileh, Dorde Jevdic

Scale-out datacenters mandate high per-server throughput to get the maximum benefit from the large TCO investment. Emerging applications (e.g., data serving and web search) that run in these datacenters operate on vast datasets that are not accommodated by ...

Ieee2012

Standard-Cell Based Memories (SCMs): from Sub-VT to Error-Resilient Systems

Andreas Peter Burg, Pascal Andreas Meinerzhagen

Embedded memories consume an increasingly dominant part of the overall area and power of a large variety of systems-on-chip [ITRS’09]: 1) biomedical implants and wireless sensor networks require robust memories operating in the sub-VT domain; 2) many handh ...

2012

One Joule per GFlop for BLAS2 Now!

Vincent Keller

Energy consumption is today one of the major topics that the HPC community tries to tackle. In this paper, the authors present a thought experiment aiming at building a node of a supercomputer based on a GPU (Nvidia GTX280). The paper concentrate on BLAS2 ...

American Institute of Physics2010

Macro-to-Microchannel Transition in Two-Phase Flow and Evaporation

Chin Lee Ong

Continuous development of highly efficient and compact cooling elements are driven by extensive developments of Micro-Electro-Mechanical Systems (MEMS) devices such as microprocessors or micro high-powered laser systems. As microprocessors continue to head ...

EPFL2010

Reputation-Based Content Dissemination for User Generated Wireless Podcasting

Jean-Yves Le Boudec

User-generated podcasting service over human-centric opportunistic network can facilitate user-generated content sharing while humans are on the move beyond the coverage of infrastructure networks. We focus on the aspects of designing efficient forwarding ...

2009

Synthesis of Predictable Networks-on-Chip Based Interconnect Architectures for Chip Multi-Processors

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali

Today, chip multiprocessors (CMPs) that accommodate multiple processor cores on the same chip have become a reality. As the communication complexity of such multicore systems is rapidly increasing, designing an interconnect architecture with predictable be ...

2007