Publications de Ajay Kumar Verma

The Red Radio Ring: a gravitationally lensed hyperluminous infrared radio galaxy at z=2.553 discovered through the citizen science project SPACE WARPS

Ajay Kumar Verma, Jean-Paul Richard Kneib

We report the discovery of a gravitationally lensed hyperluminous infrared galaxy (intrinsic L-IR approximate to 10(13) L-circle dot) with strong radio emission (intrinsic L-1.4 GHz approximate to 10(25) WHz(-1)) at z = 2.553. The source was identified in ...

Oxford University Press2015

An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

An optimal linear-time algorithm for interprocedural register allocation in high level synthesis is presented. Historically, register allocation has been modeled as a graph coloring problem, which is nondeterministic polynomial time-complete in general; ho ...

2010

Fast, Nearly Optimal ISE Identification with I/O Serialization through Maximal Clique Enumeration

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

The last decade has witnessed the emergence of the application-specific instruction-set processor (ASIP) as a viable platform for embedded systems. Extensible ASIPs allow the user to augment a base processor with instruction set extensions (ISEs) that exec ...

2010

Improving FPGA Performance for Carry-Save Arithmetic

Paolo Ienne, Ajay Kumar Verma, Philip Brisk, Hadi Parandeh Afshar

The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP applications, and further opportunities to exploit it can be exposed throug ...

2010

Pre-Synthesis Optimization of Arithmetic Circuits

Ajay Kumar Verma

The efficient synthesis of circuits is a well-studied problem. Due to the NP-hardness of the problem, no optimal algorithm has been presented so far. However, the heuristics presented by several researchers in the past, which are also adopted by commercial ...

EPFL2010

Arithmetic Optimization for Custom Instruction Set Synthesis

Paolo Ienne, Ajay Kumar Verma, Philip Brisk, Yi Zhu

One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arithmetic level. Arithmetic hardware, in many cases, can be partitioned into networks of f ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Optimistic chordal coloring: a coalescing heuristic for SSA form programs

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

The interference graph for a procedure in Static Single Assignment (SSA) Form is chordal. Since the k-colorability problem can be solved in polynomial-time for chordal graphs, this result has generated interest in SSA-based heuristics for spilling and coal ...

Springer US2009

Challenges in Automatic Optimization of Arithmetic Circuits

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open and largely unsolved problem, especially for arithmetic circuits. In many cases, the outcome of even the most adv ...

Ieee Computer Soc Press, Customer Service Center, Po Box 3014, 10662 Los Vaqueros Circle, Los Alamitos, Ca 90720-1264 Usa2009

Iterative Layering: Optimizing arithmetic circuits by structuring the information flow

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

2009

Data-flow transformations to maximize the use of carry-save representation in arithmetic circuits

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

The increasing importance,of datapath circuits in complex systems-on-chip calls for special arithmetic optimizations. The goal is to automatically achieve the handcrafted results which escape classic logic optimizations. Some work has been done in the rece ...

2008

Variable latency speculative addition: A new paradigm for arithmetic circuit design

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

Adders are one of the key components in arithmetic circuits. Enhancing their performance can significantly improve the quality of arithmetic designs. This is the reason why the theoretical lower bounds on the delay and area of an adder have been analysed, ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

Paolo Ienne, Yusuf Leblebici, Ajay Kumar Verma, Philip Brisk, Panagiotis Athanasopoulos, Alessandro Cevrero, Hadi Parandeh Afshar

The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA. To exploit the FPCA, a circuit is transformed by merging disparate addi ...

ACM2008

Fast, quasi-optimal, and pipelined instruction-set extensions

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

Nowadays many customised embedded processors offer the possibility of speeding up an application by implementing it using Application-Specific Functional units (AFUs). However, the AFUs must satisfy certain constraints in terms of read and write ports betw ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008

Progressive decomposition: A heuristic to structure arithmetic circuits

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

2007

Design of Low-Power DPA-Resistant Cryptographic Functional Units

Paolo Ienne, Yusuf Leblebici, Ajay Kumar Verma, Zeynep Toprak Deniz

2005