Publications de Seyed Armin Tajalli

ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links

Yusuf Leblebici, Seyed Armin Tajalli, Ayça Akkaya, Firat Çelik

This paper presents a comparative study, analyzing the potentials of pulse amplitude modulation (PAM) for implementing next generation high-speed copper wireline links. This comparative study analyzes the sensitivities of PAM2, PAM4 and PAM8 to inter-symbo ...

IEEE2019

A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics

Jean-Michel Sallese, Seyed Armin Tajalli, Farzan Jazaeri, Arnout Lodewijk M Beckers

Quantum computing (QC) has already entered the industrial landscape and several multinational corporations have initiated their own research efforts. So far, many of these efforts have been focusing on superconducting qubits, whose industrial progress is c ...

IEEE2019

JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS

Yusuf Leblebici, Seyed Armin Tajalli, Andreas Peter Burg, Ayça Akkaya, Firat Çelik

JESD204B compliant low-voltage differential signaling (LVDS), and source-series-terminated (SST) transmitters in 28 nm FD-SOI CMOS technology are presented with 1.1 pJ/bit and 1.7 pJ/bit at 12.5 Gb/s, respectively. An external 6.25 GHz single-ended clock, ...

IEEE2019

A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End

Yusuf Leblebici, Seyed Armin Tajalli, Ayça Akkaya, Firat Çelik

This paper presents a low power successive approximation register (SAR) ADC and its front-end automatic gain control (AGC) amplifier designed in 65nm CMOS technology. Digitally controlled variable gain amplifier (VGA) in AGC loop is used to maximize the dy ...

IEEE2018

A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links

Yusuf Leblebici, Seyed Armin Tajalli, Gain Kim, Kiarash Gharibdoust, Chen Cao

A time-division multiplexing (TDM) digital channel coding scheme with inter-symbol interference (ICI) reduction property for multi-drop memory interfaces has been proposed. Shaping the TX spectrum to avoid channel frequency notches, the proposed digital TD ...

Ieee-Inst Electrical Electronics Engineers Inc2017

A Fully-Digital Spectrum Shaping Signaling for Serial-Data Transceiver with Crosstalk and ISI Reduction Property in Multi-Drop Memory Interfaces

Yusuf Leblebici, Seyed Armin Tajalli, Gain Kim, Kiarash Gharibdoust

An efficient signaling scheme for serial-data transceivers (TRXs) has been proposed, which can properly reduce inter-symbol interference (ISI) and crosstalk (Xtalk) in memory interfaces. The proposed architecture relies on fully-digital implementation rath ...

Ieee2016

A Digital Spectrum Shaping Signaling Serial-Data Transceiver with Crosstalk and ISI Reduction Property in Multi-Drop Interfaces

Yusuf Leblebici, Seyed Armin Tajalli, Gain Kim, Kiarash Gharibdoust

A transceiver (TRX) architecture employing spectrum shaping signaling scheme is proposed, which can significantly reduce inter-symbol interference (ISI) and crosstalk in multi-drop interfaces. The proposed TRX architecture relies on digital implementation ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Jitter Analysis and Measurement in Subthreshold Source-Coupled Differential Ring Oscillators

Yusuf Leblebici, Seyed Armin Tajalli, Mahsa Shoaran

The jitter and the phase noise of ring oscillators utilizing subthreshold source-coupled logic (STSCL) style are analyzed in this paper. Closed-form equations are derived to predict the jitter and phase noise caused by white and flicker noise. Measurement ...

2015

A Subthreshold Current-Sensing Sigma-Delta Modulator for Low-Voltage and Low-Power Sensor Interfaces

Alexandre Schmid, Yusuf Leblebici, Seyed Armin Tajalli, Nikola Katic

A continuous-time (CT) ΣΔ modulator for sensing and direct analog-to-digital conversion of nA-range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source-coupled logic cells to ...

Wiley2015

Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits

Alexandre Schmid, Yusuf Leblebici, Seyed Armin Tajalli, Mahsa Shoaran

This article explores the effect of device parameter variations on the performance of subthreshold source-coupled logic (STSCL) circuits. A test chip has been fabricated in a standard CMOS 90 nm technology to study the matching properties of STSCL circuits ...

2015

A 5.43-μW 0.8-V Subthreshold Current-Sensing Σ∆ Modulator for Low-Noise Sensor Interfaces

Alexandre Schmid, Yusuf Leblebici, Seyed Armin Tajalli, Nikola Katic

A micro-watt power subthreshold current modulator suitable for low-power and low-noise sensor interfaces is presented. The prototype design is based on Subthreshold Source Coupled Logic (STSCL) cells and implemented in a 0.18 μm standard CMOS technology. T ...

2014

Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL

Yusuf Leblebici, Seyed Armin Tajalli

Power-frequency scaling in subthreshold source coupled logic (STSCL) systems has been studied and analyzed. It is shown that the operating frequency of such systems can be adjusted over about three decades with linearly proportional power dissipation. The ...

Ieee-Inst Electrical Electronics Engineers Inc2012

Methods and systems for noise resilient, pin-efficient and low power communications with sparse signaling codes

Mohammad Amin Shokrollahi, Seyed Armin Tajalli, Harm Cronie

In bus communications methods and apparatus, a first set of physical signals representing the information to be conveyed over the bus is provided, and mapped to a codeword of a sparse signaling code, wherein a codeword is representable as a vector of a plu ...

2012

Power and Area Efficient MOSFET-C Filter for Very Low Frequency Applications

Yusuf Leblebici, Seyed Armin Tajalli

New circuit design techniques for implementing very high-valued resistors are presented, significantly improving power and area efficiency of analog front-end signal processing in ultra-low power (ULP) biomedical systems. Ranging in value from few hundreds ...

Springer Verlag2012

Design trade-offs in ultra-low-power CMOS and STSCL digital systems

Yusuf Leblebici, Seyed Armin Tajalli

2011

Low-Power and Widely-Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter

Yusuf Leblebici, Seyed Armin Tajalli

A sixth-order low-pass

g_m

-C filter with a very wide tuning range (

f_c

= 100 Hz to 10 MHz) is presented. The wide tuning range has been achieved without using switchable components or programmable building blocks. A single stage folded-cascode transcon ...

Institute of Electrical and Electronics Engineers2011

Design Tradeoffs in Ultra-Low-Power Digital Nano-Scale CMOS

Yusuf Leblebici, Seyed Armin Tajalli

In ultra-low-power (ULP) applications, the supply voltage is generally reduced well below threshold voltage of MOS devices in order to limit dissipation and to control the device leakage current due to the subthreshold channel residual current. However, re ...

Institute of Electrical and Electronics Engineers2011

An area and power optimization technique for CMOS bandgap voltage references

Seyed Armin Tajalli, Mohammad Chahardori

This article explores the main tradeoffs in design of power and area efficient bandgap voltage reference (BGR) circuits. A structural design methodology for optimizing the silicon area and power dissipation of CMOS BGRs will be introduced. For this purpose ...

Springer US2010

A 9 pW/Hz Adjustable Clock Generator with 3-Decade Tuning Range for Dynamic Power Management in Subthreshold SCL Systems

Yusuf Leblebici, Seyed Armin Tajalli

A widely-tunable and power-scalable clock generator for ultra-low power (ULP) applications is presented. Benefitting from a novel self-adjustable loop frequency response, the proposed phase-locked loop based clock generator exhibits a tuning range of three ...

2010

Ultra-Low Power Mixed-Signal Design Platform Using Subthreshold Source-Coupled Circuits

Yusuf Leblebici, Seyed Armin Tajalli

This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultra-low power power-scalable analog and digital integrated circuits. The proposed techniq ...

DATE2010