Publications de Philip Brisk | EPFL Graph Search

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Philip Brisk, Mirjana Stojilovic, Frédéric Gessler

RePlAce is a state-of-the-art prototype of a flat, analytic, and nonlinear global cell placement algorithm, which models a placement instance as an electrostatic system with positively charged objects. It can handle large-scale standard-cell and mixed-cell ...

IEEE2020

Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model

Philip Brisk, Mirjana Stojilovic

This paper describes a deterministic and parallel implementation of the VPR routability-driven router for FPGAs. We considered two parallefization strategies: (1) routing multiple nets in parallel; and (2) routing one net at a time, while parallelizing the ...

IEEE2018

An Out-of-Order Load-Store Queue for Spatial Computing

Paolo Ienne, Philip Brisk, Lana Josipovic

The efficiency of spatial computing depends on the ability to achieve maximal parallelism. This necessitates memory interfaces that can correctly handle memory accesses that arrive in arbitrary order while still respecting data dependencies and ensuring ap ...

Assoc Computing Machinery2017

From C to elastic circuits

Paolo Ienne, Philip Brisk, Lana Josipovic

2017

Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking

Paolo Ienne, Philip Brisk, Andrew James Becker, Wei Hu, Ryan Charles Kastner

2017

Automatic Application of Power Analysis Countermeasures

Paolo Ienne, Philip Brisk, Francesco Regazzoni, Ali Galip Bayrak, David Novo Bruna

We introduce a compiler that automatically inserts software countermeasures to protect cryptographic algorithms against power-based side-channel attacks. The compiler first estimates which instruction instances leak the most information through side-channe ...

Institute of Electrical and Electronics Engineers2015

Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage

Paolo Ienne, Edoardo Charbon, Ties Jan Henderikus Kluter, Samuel Burri, Philip Brisk

Instruction set extensions (ISEs) improve the performance and energy consumption of application-specific processors. ISEs can use architecturally visible storage (AVS), localized compiler-controlled memories, to provide higher I/O bandwidth than reading da ...

Assoc Computing Machinery2014

Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions

Paolo Ienne, Edoardo Charbon, Ties Jan Henderikus Kluter, Philip Brisk

Way Stealing is a simple architectural modification to a cache-based processor that increases the data bandwidth to and from application-specific instruction set extensions (ISEs), which increase performance and reduce energy consumption. Way Stealing offe ...

Institute of Electrical and Electronics Engineers2014

Generalized programmable counter arrays

Philip Brisk, Alessandro Cevrero, Hadi Parandeh Afshar

A Generalized Programmable Counter Array (GPCA) is a reconfigurable multi-operand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to compress the input words down to two operands using parallel coun ...

2014

Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays

Paolo Ienne, Philip Brisk, David Novo Bruna, Mirjana Stojilovic

Historically, hardware acceleration technologies have either been application-specific, therefore lacking in flexibility, or fully programmable, thereby suffering from notable inefficiencies on an application-by-application basis. To address the growing ne ...

Institute of Electrical and Electronics Engineers2013

Compressor Tree Synthesis on Commercial High-Performance FPGAs

Paolo Ienne, Philip Brisk, Hadi Parandeh Afshar

Compressor trees are a class of circuits that generalizes multioperand addition and the partial product reduction trees of parallel multipliers using carry-save arithmetic. Compressor trees naturally occur in many DSP applications, such as FIR filters, and ...

2011

An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

An optimal linear-time algorithm for interprocedural register allocation in high level synthesis is presented. Historically, register allocation has been modeled as a graph coloring problem, which is nondeterministic polynomial time-complete in general; ho ...

2010

Improving FPGA Performance for Carry-Save Arithmetic

Paolo Ienne, Ajay Kumar Verma, Philip Brisk, Hadi Parandeh Afshar

The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP applications, and further opportunities to exploit it can be exposed throug ...

2010

Fast, Nearly Optimal ISE Identification with I/O Serialization through Maximal Clique Enumeration

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

The last decade has witnessed the emergence of the application-specific instruction-set processor (ASIP) as a viable platform for embedded systems. Extensible ASIPs allow the user to augment a base processor with instruction set extensions (ISEs) that exec ...

2010

MPSoC Design using Application-Specific Architecturally Visible Communication

Paolo Ienne, Edoardo Charbon, Ties Jan Henderikus Kluter, Philip Brisk

This paper advocates the placement of Architecturally Visible Communication (AVC) buffers between adjacent cores in MPSoCs to provide high-throughput communication for streaming applications. Producer/consumer relationships map poorly onto cache-based MPSo ...

Springer-Verlag2009

Arithmetic Optimization for Custom Instruction Set Synthesis

Paolo Ienne, Ajay Kumar Verma, Philip Brisk, Yi Zhu

One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arithmetic level. Arithmetic hardware, in many cases, can be partitioned into networks of f ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Optimistic chordal coloring: a coalescing heuristic for SSA form programs

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

The interference graph for a procedure in Static Single Assignment (SSA) Form is chordal. Since the k-colorability problem can be solved in polynomial-time for chordal graphs, this result has generated interest in SSA-based heuristics for spilling and coal ...

Springer US2009

Memory Organization and Data Layout for Instruction Set Extensions with Architecturally Visible Storage

Paolo Ienne, Yusuf Leblebici, Philip Brisk, Panagiotis Athanasopoulos

Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional units (CFUs). Adoption of the optimal ISE for an application would, in many cas ...

2009

Challenges in Automatic Optimization of Arithmetic Circuits

Paolo Ienne, Ajay Kumar Verma, Philip Brisk

Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open and largely unsolved problem, especially for arithmetic circuits. In many cases, the outcome of even the most adv ...

Ieee Computer Soc Press, Customer Service Center, Po Box 3014, 10662 Los Vaqueros Circle, Los Alamitos, Ca 90720-1264 Usa2009

Exploiting Fast Carry-Chains Of Fpgas For Designing Compressor Trees

Paolo Ienne, Philip Brisk, Hadi Parandeh Afshar

Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic blocks of FPGAs for fast addition. Conventional intuition is that such carry c ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009