Alessandro Cevrero

Cette personne n’est plus à l’EPFL

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Publications associées (32)

3D-MMC: A Modular 3D Multi-Core Architecture with Efficient Resource Pooling

Yusuf Leblebici, Ayse Kivilcim Coskun, Panagiotis Athanasopoulos, Alessandro Cevrero, Giulia Beanato

2013

Fast and Accurate BER Estimation Methodology for I/O Links based on Extreme Value Theory

Paolo Ienne, Yusuf Leblebici, Alessandro Cevrero, Andreas Peter Burg

2013

A Parallelized Layered QC-LDPC Decoder for IEEE 802.11ad

Alessandro Cevrero, Andreas Peter Burg, Nicholas Alexander Preyss, Alexios Konstantinos Balatsoukas Stimming

We present a doubly parallelized layered quasi-cyclic low density parity-check decoder for the emerging IEEE 802.11ad multigigabit wireless standard. The decoding algorithm is equivalent to a nonparallelized layered decoder and, thus, retains its favorable ...

IEEE2013

Towards Cost Effective Multi-Core Processor Platforms Using 3-D Stacking Technology

Yusuf Leblebici, Panagiotis Athanasopoulos, Alessandro Cevrero, Giulia Beanato

A novel modular, cost e ffective 3D multi-processor architecture is presented. Auto-configurable and independently testable identical dies are stacked exploiting Through-Silicon-Vias (TSV) technology, allowing to target different market segments by selecti ...

2012

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

Yusuf Leblebici, Panagiotis Athanasopoulos, Michail Zervas, Alessandro Cevrero, Yüksel Temiz, Giulia Beanato, Paolo Giovannini

An innovative modular 3-D stacked multi-processor architecture is presented. The platform is composed of completely identical stacked dies connected together by through-silicon-vias (TSVs). Each die features four 32-bit embedded processors and associated m ...

2012

A 3D Stacked Multi-Core Processor Platform with Improved Testability

Yusuf Leblebici, Panagiotis Athanasopoulos, Alessandro Cevrero, Giulia Beanato, Paolo Giovannini

2012

Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders

Yusuf Leblebici, Alessandro Cevrero, Christoph Studer, Andreas Peter Burg

2011

Design and Feasibility of Multi-Gb/s Quasi-Serial Vertical Interconnects based on TSVs for 3D ICs

Yusuf Leblebici, Panagiotis Athanasopoulos, Alessandro Cevrero, Fengda Sun

This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced by serialized links to save silicon area and increase yield. Detailed analysis ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2010

A 5.35 mm2 10GBASE-T Ethernet LDPC Decoder Chip in 90 nm CMOS

Paolo Ienne, Yusuf Leblebici, Alessandro Cevrero, Andreas Peter Burg

A partially parallel low density parity check (LDPC) decoder compliant with the IEEE 802.3an standard for 10GBASE-T Ethernet is presented. The design is optimized for minimum silicon area and is based on the layered offset-min-sum algorithm which speeds up ...

2010

Using 3D Integration Technology To Realize Multi-Context Fpgas

Paolo Ienne, Yusuf Leblebici, Maurizio Skerlj, Philip Brisk, Alessandro Cevrero, Hadi Parandeh Afshar

This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a latch array on the DRAM layer while the FPGA executes; the new configuration ...

IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, NJ 08855-1331 USA2009

Design Space Exploration for Field Programmable Compressor Trees

Paolo Ienne, Yusuf Leblebici, Philip Brisk, Alessandro Cevrero

2008

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

Paolo Ienne, Yusuf Leblebici, Ajay Kumar Verma, Philip Brisk, Panagiotis Athanasopoulos, Alessandro Cevrero, Hadi Parandeh Afshar

The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA. To exploit the FPCA, a circuit is transformed by merging disparate addi ...

ACM2008

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