Publications de David Novo Bruna

Design Space Exploration of LDPC Decoders Using High-Level Synthesis

Paolo Ienne, Vitor Silva, Nithin George, David Novo Bruna, Gabriel Falcao Paiva Fernandes, João Maria Duarte Andrade

2017

FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures

Paolo Ienne, David Novo Bruna, Grace Zgheib, Manana Lortkipanidze

2016

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Paolo Ienne, Andreas Peter Burg, David Novo Bruna, Madhura Purnaprajna, Georgios Karakonstantis, Gabriel Falcao Paiva Fernandes, João Maria Duarte Andrade

The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI implementatio ...

Assoc Computing Machinery2015

Automatic Application of Power Analysis Countermeasures

Paolo Ienne, Philip Brisk, Francesco Regazzoni, Ali Galip Bayrak, David Novo Bruna

We introduce a compiler that automatically inserts software countermeasures to protect cryptographic algorithms against power-based side-channel attacks. The compiler first estimates which instruction instances leak the most information through side-channe ...

Institute of Electrical and Electronics Engineers2015

Libra: Software-Controlled Cell Bit-Density to Balance Wear in NAND Flash

Paolo Ienne, Xavier Jimenez, David Novo Bruna

Hybrid flash storages combine a small Single-Level Cell (SLC) partition with a large Multilevel Cell (MLC) partition. Compared to MLC-only solutions, the SLC partition exploits fast and short local write updates, while the MLC part brings large capacity. O ...

Assoc Computing Machinery2015

Majority-Inverter Graph for FPGA Synthesis

Paolo Ienne, Giovanni De Micheli, Ana Petkovska, David Novo Bruna, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon

In this paper, we present an FPGA synthesis flow based on Majority-Inverter Graph (MIG). An MIG is a directed acyclic graph consisting of three-input majority nodes and regular/complemented edges. MIG manipulation is supported by a consistent alge ...

2015

A technology mapper for depth-constrained FPGA logic cells

Paolo Ienne, David Novo Bruna, Grace Zgheib

2015

Automatic support for multi-module parallelism from computational patterns

Paolo Ienne, Nithin George, David Novo Bruna, David Loyd Andrews

2015

From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis

Paolo Ienne, Vitor Silva, Nithin George, David Novo Bruna, Gabriel Falcao Paiva Fernandes, João Maria Duarte Andrade

2015

FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction

Paolo Ienne, Barbara Jobstmann, David Novo Bruna, Andrew James Becker, Mohsen A A Ewaida

Functional verification occupies a significant amount of the digital circuit design cycle. In this paper, we present a novel approach to improve circuit debugging which not only localizes errors with high confidence, but can also provide semantically-meani ...

Springer2015

Improved carry chain mapping for the VTR flow

Paolo Ienne, Ana Petkovska, David Novo Bruna, Grace Zgheib

Carry chains facilitate the implementation of adders and improve the performance of arithmetic circuits in FPGAs. The last version of the commonly used open-source Verilog-to-Routing (VTR) CAD flow now enables modelling carry chains in FPGA architectures. ...

IEEE2015

Non-LUT field-programmable gate arrays

Paolo Ienne, Hadi Parandeh Afshar, David Novo Bruna, Grace Zgheib

New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels ...

2014

Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays

Paolo Ienne, Philip Brisk, David Novo Bruna, Mirjana Stojilovic

Historically, hardware acceleration technologies have either been application-specific, therefore lacking in flexibility, or fully programmable, thereby suffering from notable inefficiencies on an application-by-application basis. To address the growing ne ...

Institute of Electrical and Electronics Engineers2013

Cracking The Complexity Of Fixed-Point Refinement In Complex Wireless Systems

Paolo Ienne, David Novo Bruna

Fixed-point arithmetic leads to efficient implementations. However, the optimization process required to size each of the implementation signals can be prohibitively complex. In this paper, we introduce a new divide-and-conquer method that is able to appro ...

Ieee2013

Software Controlled Cell Bit-Density to Improve NAND Flash Lifetime

Paolo Ienne, Xavier Jimenez, David Novo Bruna

Hybrid flash architectures combine static partitions in Sing le Level Cell (SLC) mode with partitions in Multi Level Cell (MLC) mode. Compared to MLC-only solutions, the former exploits fast and short random writes while the latter brings large capacity. O ...

Ieee2012

Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case

Paolo Ienne, Andreas Peter Burg, David Novo Bruna, Madhura Purnaprajna, Georgios Karakonstantis, Gabriel Falcao Paiva Fernandes

Hardware designers and engineers typically need to explore a multi-parametric design space in order to ﬁnd the best conﬁguration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips ...

2012