Publications de Giovanni Ansaloni

A Reconfigurable High-Dynamic Range ∆Σ Front-End with Event-Based Decimation for Bandwidth-Efficient Implantable Neural Interfaces

David Atienza Alonso, Giovanni Ansaloni, Pasquale Davide Schiavone, Juan Pablo Sapriza Araujo

As the demand for high channel counts and high-resolution recordings of neural activity continues to grow, the increased power and data rate generated impose hard constraints on the telemetry capabilities of wireless implantable neural interfaces. To addre ...

IEEE2025

HEEPstor: an Open-Hardware Co-design Framework for Quantized Machine Learning at the Edge

David Atienza Alonso, Giovanni Ansaloni, Rafael Medina Morillas

Edge-AI applications necessitate the joint application of hardware acceleration and software optimization to meet energy and area constraints. However, the co-design of these systems is hindered by the lack of integration options for novel hardware prototy ...

ACM2025

Keep All in Memory with Maxwell: a Near-SRAM Computing Architecture for Edge AI Applications

David Atienza Alonso, Giovanni Ansaloni, Grégoire Axel Eggermann

Recent advances in machine learning have dramatically increased model size and computational requirements, increasingly straining computing system capabilities. This tension is particularly acute for resource-constrained edge scenarios, for which careful h ...

IEEE2025

LIONHEART: A Layer-based Mapping Framework for Heterogeneous Systems with Analog In-Memory Computing Tiles

David Atienza Alonso, Giovanni Ansaloni, Irem Boybat Kara, Marina Zapater Sancho, Abu Sebastian, Flavio Ponzina, Joshua Alexander Harrison Klein

When arranged in a crossbar configuration, resistive memory devices can be used to execute Matrix-Vector Multiplications (MVMs), the most dominant operation of many Machine Learning (ML) algorithms, in constant time complexity. Nonetheless, when performing ...

Institute of Electrical and Electronics Engineers (IEEE)2025

Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems

David Atienza Alonso, Giovanni Ansaloni, Rafael Medina Morillas

Efficient deployment of resource-intensive transformers on edge devices necessitates cross-stack optimization. We thus study the interrelation between structured pruning and systolic acceleration, matching the size of pruned blocks with the systolic array ...

Association for Computing Machinery2025

SideDRAM: Integrating SoftSIMD Datapaths near DRAM Banks for Energy-Efficient Variable Precision Computation

David Atienza Alonso, Giovanni Ansaloni, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Rafael Medina Morillas, Pengbo Yu

By interfacing computing logic directly to the DRAM banks, bank-level Compute-near-Memory (CnM) architectures promise to mitigate the bottleneck at the memory interconnect. While this computation paradigm heavily reduces the energy requirements for data mo ...

ACM2025

Towards Accurate RISC-V Full System Simulation via Component-level Calibration

David Atienza Alonso, Giovanni Ansaloni, Marina Zapater Sancho, Joshua Alexander Harrison Klein

Full-System (FS) simulation is essential for performance evaluation of complete systems that execute complex applications on a complete software stack consisting of an operating system and user applications. Nevertheless, they require careful fine-tuning a ...

Association for Computing Machinery (ACM)2025

A Reconfigurable High Dynamic Range Delta-Sigma Front End with Event-Based Decimation for Bandwidth-EfficientImplantable Neural Interfaces

David Atienza Alonso, Giovanni Ansaloni, Pasquale Davide Schiavone, Juan Pablo Sapriza Araujo

As the demand for high channel counts and high-resolution recordings of neural activity continues to grow, the increased power and data rate generated impose hard constraints on the telemetry capabilities of wireless implantable neural interfaces. To addre ...

2025

An MLIR-based Compilation Framework for CGRA Application Deployment

David Atienza Alonso, Giovanni Ansaloni, Lara Orlandic, Juan Pablo Sapriza Araujo, Rubén Rodríguez Álvarez

Coarse-Grained Reconfigurable Arrays (CGRAs) are a programmable architectural solution that efficiently supports the execution of computation-intensive application functions (kernels). Compilers for CGRAs typically focus on optimizing the mapping of single ...

2025

A flexible framework for early power and timing comparison of time-multiplexed CGRA kernel executions

David Atienza Alonso, Giovanni Ansaloni, Juan Pablo Sapriza Araujo

At the intersection between traditional CPU architectures and more specialized options such as FPGAs or ASICs lies the family of reconfigurable hardware architectures, termed Coarse-Grained Reconfigurable Arrays (CGRAs). CGRAs are composed of a 2-dimension ...

ACM2025

DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD

Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Flavio Ponzina, Pengbo Yu

Machine learning algorithms such as Convolutional Neural Networks (CNNs) are characterized by high robustness towards quantization, supporting small-bitwidth fixed-point arithmetic at inference time with little to no degradation in accuracy. In turn, small ...

IEEE2024

Cross-layer Exploration of 2.5D Energy-Efficient Heterogeneous Chiplets Integration: From System Simulation to Open Hardware

David Atienza Alonso, Giovanni Ansaloni, Miguel Peon Quiros, Anna Burdina, Pasquale Davide Schiavone

In the past decade, computing systems have significantly increased in complexity and power consumption. Nowadays, heterogeneous multi-processor systems-on-chip (MPSoCs) integrate many computing cores. Heterogeneous MPSoCs often comprise general-purpose pro ...

Association for Computing Machinery, Inc2024

Bank on Compute-near-Memory: Design Space Exploration of Processing-near-Bank Architectures

Giovanni Ansaloni, Marina Zapater Sancho, Rafael Medina Morillas

Near-DRAM computing strategies advocate for providing computational capabilities close to where data is stored. Although this paradigm can effectively address the memoryto-processor communication bottleneck, it also presents new challenges: The strict reso ...

Institute of Electrical and Electronics Engineers (IEEE)2024

Which Coupled is Best Coupled? An Exploration of AIMC Tile Interfaces and Load Balancing for CNNs

David Atienza Alonso, Giovanni Ansaloni, Irem Boybat Kara, Joshua Alexander Harrison Klein

Due to stringent energy and performance constraints, edge AI computing often employs heterogeneous systems that utilize both general-purpose CPUs and accelerators. Analog in-memory computing (AIMC) is a well-known AI inference solution that overcomes compu ...

Institute of Electrical and Electronics Engineers (IEEE)2024

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

David Atienza Alonso, Giovanni Ansaloni, Alireza Amirshahi

The increasing complexity of transformer models in artificial intelligence expands their computational costs, memory usage, and energy consumption. Hardware acceleration tackles the ensuing challenges by designing processors and accelerators tailored for t ...

2024

An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Flavio Ponzina, Pengbo Yu

The ever-increasing computational complexity and energy consumption of today's applications, such as Machine Learning (ML) algorithms, not only strain the capabilities of the underlying hardware but also significantly restrict their wide deployment at the ...

2024

SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs

Ruben Rodriguez, David Atienza Alonso, Benoît Walter Denkinger, Giovanni Ansaloni, José Angel Miranda Calero, Juan Pablo Sapriza Araujo, Rubén Rodríguez Álvarez

Coarse-Grain Reconfigurable Arrays (CGRAs) represent emerging low-power architectures designed to accelerate Compute-Intensive Loops (CILs). The effectiveness of CGRAs in providing acceleration relies on the quality of mapping: how efficiently the CIL is c ...

2024

Resource-Efficient Continual Learning for Personalized Online Seizure Detection

David Atienza Alonso, Giovanni Ansaloni, Flavio Ponzina, Amirhossein Shahbazinia, José Angel Miranda Calero, Jonathan Dan

Epilepsy, a major neurological disease, requires careful diagnosis and treatment. However, the detection of epileptic seizures remains a significant challenge. Current clinical practice relies on expert analysis of EEG signals, a process that is time-consu ...

IEEE2024

FVLLMONTI: The 3D Neural Network Compute Cube (N2C2) Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation

David Atienza Alonso, Giovanni Ansaloni, Alireza Amirshahi

This multi-partner-project contribution introduces the midway results of the Horizon 2020 FVLLMONTI project. In this project we develop a new and ultra-efficient class of ANN accelerators, the neural network compute cube (N2C2), which is specifically desig ...

Institute of Electrical and Electronics Engineers Inc.2024

ACE: Automated optimization towards iterative Classification in Edge health monitors

David Atienza Alonso, Giovanni Ansaloni, Lara Orlandic, Simone Machetti

Wearable devices for health monitoring are essential for tracking individuals' health status and facilitating early detection of diseases. However, processing biomedical signals online for real-time monitoring is challenging due to limited computational re ...

Institute of Electrical and Electronics Engineers (IEEE)2024