Publications de Andrea Bonetti

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman, Robert Giterman

The rise of data-intensive applications has resulted in an increasing demand for high-density and low-power on-chip embedded memories. Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible alternative to conventional static random access memory (SRAM) w ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Gain-Cell Embedded DRAMs: Modeling and Design Space

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman, Robert Giterman

Among the different types of DRAMs, gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power and CMOS-compatible alternative to conventional SRAM. GC-eDRAM achieves high memory density as it relies on a storage cell that can be implemented with as few as ...

IEEE2020

Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices

David Atienza Alonso, Andreas Peter Burg, Martino Ruggiero, Benoît Walter Denkinger, Soumya Subhra Basu, Andrea Bonetti, Szabolcs Balási, Miguel Peon Quiros, Flavio Ponzina

Energy consumption is a significant obstacle to integrate deep learning into edge devices. Two common techniques to curve it are quantization, which reduces the size of the memories (static energy) and the number of accesses (dynamic energy), and voltage s ...

2020

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman, Robert Giterman

Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to conventional SRAM due to its high-density, low-leakage, and inherent two-ported functionality. However, its dynamic storage mechanism requires power-hungry refresh cycles to maintain data. ...

IEEE2020

Gain-Cell Embedded DRAMs: Modeling and Design Space

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman, Robert Giterman

Among the different types of dynamic random-access memories (DRAMs), gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power, and CMOS-compatible alternative to conventional static random-access memory (SRAM). GC-eDRAM achieves high memory density, as i ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

Andrea Bonetti

As an increase of intelligent and self-powered devices is forecasted for our future everyday life, the implementation of energy-autonomous devices that can wirelessly communicate data from sensors is crucial. Even though techniques such as voltage scaling ...

EPFL2019

GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman, Robert Giterman

Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to conventional SRAM due to its high-density, low-leakage, and inherent two-ported functionality. However, its dynamic storage mechanism requires power-hungry refresh cycles to maintain data. ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Data-Retention-Time Characterization of Gain-Cell eDRAMs across the Design and Variations Space

Andreas Peter Burg, Andrea Bonetti

The rise of data-intensive applications has increased the demand for high-density and low-power embedded memories. Among them, the gain-cell embedded DRAM (GC-eDRAM) is a suitable alternative to the static random access memory (SRAM) due to its high memory ...

IEEE2019

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications

Yusuf Leblebici, Andreas Peter Burg, Cosimo Aprile, Andrea Bonetti, Nicolas Claude Frigerio, Robert Giterman, Jonathan Emmanuel D Narinx

Logic-compatible gain-cell embedded DRAM (GC-eDRAM) is an emerging alternative to conventional SRAM for memory-dominated system-on-chip (SoC) designs due to its high-density, low-power, and two-ported operation. Although GCs have a limited data retention t ...

IEEE2019

FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems

Andreas Peter Burg, Andrea Bonetti, Marco Widmer

Embedded DRAM (eDRAM) requires frequent power-hungry refresh according to the worst-case retention time across PVT variations to avoid data loss. Abandoning the error-free paradigm, by choosing sub-critical refresh rates that gracefully degrade the eDRAM c ...

ASSOC COMPUTING MACHINERY2019

A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI

Andreas Peter Burg, Jeremy Hugues-Felix Constantin, Andrea Bonetti, Adam Shmuel Teman

The increasing impact of variability on near-threshold nanometer circuits calls for a tighter online monitoring and control of the available timing margins. Error-detection sequentials are widely used together with error-correction techniques to operate di ...

IEEE2018

Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman

Reconfigurable finite-impulse response (FIR) filters are one of the most widely implemented components in Internet of Things systems that require flexibility to support several target applications while consuming the minimum amount of power to comply with ...

Ieee-Inst Electrical Electronics Engineers Inc2017

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes

Andreas Peter Burg, Nicholas Alexander Preyss, Andrea Bonetti, Adam Shmuel Teman

Clocking power, including both clock distribution and registers, has long been one of the primary factors in the total power consumption of many digital systems. One straightforward approach to reduce this power consumption is to apply dual-edge-triggered ...

Association for Computing Machinery2017

PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Andrea Bonetti, Thomas Christoph Müller, Pascal Giard

Polar codes are a recently proposed class of block codes that provably achieve the capacity of various communication channels. They received a lot of attention as they can do so with low-complexity encoding and decoding algorithms, and they have an explici ...

2017

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Lorenz Flavio Schmid, Jeremy Hugues-Felix Constantin, Andrea Bonetti, Adam Shmuel Teman, Thomas Christoph Müller

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

Refresh-Free Dynamic Standard-Cell Based Memories: Application to a QC-LDPC Decoder

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Georgios Karakonstantis, Andrea Bonetti

The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated w ...

2015