Publications de Andrea Guerrieri

DRSA: Accelerating Macro Placement on Commercial FPGAs

Paolo Ienne, Lana Josipovic, Andrea Guerrieri

PGAs are highly versatile devices, but their backend compilation process is significantly time-consuming. DynaRapid has demonstrated the potential to drastically reduce compilation times to mere seconds by leveraging macro-component-based design hierarchie ...

IEEE2025

Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Ayatallah Ahmed Gamal Kamal Elakhras

Dynamically scheduled HLS, through dataflow circuit generation, has proven successful at exploiting operation-level parallelism in several important situations where statically scheduled HLS fails. Yet, although existing dataflow circuits support out-of-or ...

Association for Computing Machinery, Inc2024

Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits

Andrea Guerrieri

High-level synthesis (HLS) tools generate hardware designs from high-level software languages while sidestepping intricate low-level hardware details. However, HLS tools struggle with precise dynamic power estimation and optimization: the high abstraction ...

Institute of Electrical and Electronics Engineers Inc.2024

Blending Scheduling Barriers: A Hybrid Approach for FPGA-based Post-Quantum Cryptography

Andrea Guerrieri

FPGAs hold great promises for Post-Quantum Cryptography (PQC) hardware through the adoption of electronic design automation tools such as High-Level Synthesis (HLS). Previous works demonstrated how the combination of pragmas and code refactoring techniques ...

IEEE2024

Where is M-theory in the space of scattering amplitudes?

João Miguel Augusto Penedones Fernandes, Andrea Guerrieri

We use the S-matrix bootstrap to carve out the space of unitary, analytic, crossing symmetric and supersymmetric graviton scattering amplitudes in nine, ten and eleven dimensions. We extend and improve the numerical methods of our previous work in ten dime ...

Springer Nature2023

Resource Sharing in Dataflow Circuits

Paolo Ienne, Lana Josipovic, Andrea Guerrieri, Axel Marmet

To achieve resource-efficient hardware designs, high-level synthesis (HLS) tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed in conjunction with operation scheduling to ensure th ...

Assoc Computing Machinery2023

An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits

Lana Josipovic, Andrea Guerrieri, Carmine Rizzi

Dataflow circuits promise to overcome the scheduling limitations of standard HLS solutions. However, their performance suffers due to timing overheads caused by their handshake communication protocol. Current pipelining solutions fail to account for logic ...

IEEE2023

Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Ayatallah Ahmed Gamal Kamal Elakhras

Dynamically scheduled high-level synthesis can exploit high levels of parallelism in poorly-predictable control-dominated applications. Yet, dataflow circuits are often generated by literal conversion of basic blocks into circuits interconnected in such a ...

Assoc Computing Machinery2023

Numerical data for scattering amplitudes of Neutral Goldstone bosons in 4d

Kelian Philippe Häring, Andrea Guerrieri, Denis Karateev

Numerical data for scattering amplitudes of Goldstone bosons in d=4 obtained by solving various optimisation problems. The data is stored in .m files. Mathematica notebook is provided for loading and plotting the data. ...

Zenodo2023

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits

Paolo Ienne, Lana Josipovic, Andrea Guerrieri, Carmine Rizzi

The ability of dataflow circuits to implement dynamic scheduling promises to overcome the conservatism of static scheduling techniques that high-level synthesis tools typically rely on. Yet, the same distributed control mechanism that allows dataflow circu ...

IEEE COMPUTER SOC2022

Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level Synthesis

Andres Upegui, Francesco Regazzoni, Andrea Guerrieri

High-level synthesis is a mature Electronics Design Automation (EDA) technology for building hardware design in a short time. It produces automatically HDL code for FPGAs out of C/C++, bridging the gap from algorithm to hardware. Nevertheless, sometimes th ...

IEEE2022

From C/C plus plus Code to High-Performance Dataflow Circuits

Paolo Ienne, Lana Josipovic, Andrea Guerrieri

High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Resource Sharing in Dataflow Circuits

Paolo Ienne, Lana Josipovic, Andrea Guerrieri, Axel Marmet

To achieve resource-efficient hardware designs, HLS tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed together with operation scheduling to ensure the best possible unit usage at ...

IEEE2022

Unleashing Parallelism in Elastic Circuits with Faster Token Delivery

Paolo Ienne, Lana Josipovic, Andrea Guerrieri, Ayatallah Ahmed Gamal Kamal Elakhras

High-level synthesis (HLS) is the process of automatically generating circuits out of high-level language descriptions. Previous research has shown that dynamically scheduled HLS through elastic circuit generation is successful at exploiting parallelism in ...

IEEE COMPUTER SOC2022

Buffer Placement and Sizing for High-Performance Dataflow Circuits

Paolo Ienne, Lana Josipovic, Andrea Guerrieri, Shabnam Sheikhha

2022

Where Is String Theory in the Space of Scattering Amplitudes?

João Miguel Augusto Penedones Fernandes, Andrea Guerrieri

We use the S-matrix bootstrap to carve out the space of unitary, crossing symmetric and supersymmetric graviton scattering amplitudes in ten dimensions. We focus on the leading Wilson coefficient a controlling the leading correction to maximal supergravity ...

AMER PHYSICAL SOC2021

Synthesizing General-Purpose Code Into Dynamically Scheduled Circuits

Paolo Ienne, Lana Josipovic, Andrea Guerrieri

Since their inception more than thirty years ago, field-programmable gate arrays (FPGAs) have been widely used to implement a myriad of applications from different domains. As a result of their low-level hardware reconfigurability, FPGAs have much faster d ...

2021

Resource Sharing in Dataflow Circuits

Paolo Ienne, Lana Josipovic, Andrea Guerrieri, Axel Marmet

2021

Invited Tutorial Dynamatic: From C/C plus plus to Dynamically Scheduled Circuits

Paolo Ienne, Lana Josipovic, Andrea Guerrieri

High-level synthesis tools, both commercial and academic, typically rely on static scheduling to produce high-throughput pipelines. However, in applications with unpredictable memory accesses or irregular control flow, these tools need to make pessimistic ...

ASSOC COMPUTING MACHINERY2020

Buffer Placement and Sizing for High-Performance Dataflow Circuits

Paolo Ienne, Lana Josipovic, Andrea Guerrieri, Shabnam Sheikhha

Commercial high-level synthesis tools typically produce statically scheduled circuits. Yet, effective C-to-circuit conversion of arbitrary software applications calls for dataflow circuits, as they can handle efficiently variable latencies (e.g., caches) a ...

ASSOC COMPUTING MACHINERY2020