Publications associées à A Real-Time Compressed Sensing-Based Personal Electrocardiogram Monitoring System

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Mirjana Stojilovic, Ognjen Glamocanin, Mathias Josef Payer, Shashwat Shrivastava, Jinwei Yao, Nour Ardo

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

2023

Fast Energy Estimation Through Partial Execution of HPC Applications

José Luis Ayala Rodrigo, Marina Zapater Sancho

In order to optimize the energy use of servers in Data Centers, techniques such as power capping or power budgeting are usually deployed. These techniques rely on the prediction of the power and execution time of applications. These data are obtained via d ...

IEEE2018

IoT for Telemedicine Practices enabled by an Android (TM) Application with Cloud System Integration

Sandro Carrara, Thiébaud Modoux, Francesca Stradolini, Abuduwaili Tuoheti, Danilo Demarchi, Nadia Tamburrano

Connected medical devices are already paving the way towards the realization of Smart Hospitals where patient care is improved thanks to Internet of Things (IoT) solutions. Following this trend, in this paper we propose an IoT cloud-based network for anest ...

IEEE2018

Trading off Energy versus Accuracy in Modern Computing Systems : From Digital Circuit Design to Programming Techniques

Jérémy Lucien Maurice Schlachter

The slowdown of Moore's law, which has been the driving force of the electronics industry over the last 5 decades, is causing serious problem to Integrated Circuits (ICs) improvements. Technology scaling is becoming more and more complex and fabrication co ...

EPFL2018

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Lorenz Flavio Schmid, Jeremy Hugues-Felix Constantin, Andrea Bonetti, Adam Shmuel Teman, Thomas Christoph Müller

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

Attaining Single-Chip, High-Performance Computing Through 3D Systems with Active Cooling

David Atienza Alonso, Ayse Kivilcim Coskun, Mohamed Mostafa Sabry Aly, Jie Meng

Three-dimensional (3D) stacking is an attractive method for designing large manycore chips as it provides high transistor integration densities, improves manufacturing yield due to smaller chip area, reduces wirelength and capacitance, and enables heteroge ...

Institute of Electrical and Electronics Engineers2011

Real-Time Compressed Sensing-Based Electrocardiogram Compression on Energy Constrained Wireless Body Sensors

Pierre Vandergheynst, David Atienza Alonso, Nadia Khaled, Hossein Mamaghanian

Wireless body sensor networks (WBSN) hold the promise to enable next-generation patient-centric tele-cardiology systems. A WBSNenabled electrocardiogram (ECG) monitor consists of wearable, miniaturized and wireless sensors able to measure and wirelessly re ...

IEEE Press2011

Platform-independent profiling in a virtual execution environment

Philippe Moret

Virtual execution environments, such as the Java virtual machine, promote platform-independent software development. However, when it comes to analyzing algorithm complexity and performance bottlenecks, available tools focus on platform-specific metrics, s ...

2008

Temperature-Aware Processor Frequency Assignment for MPSoCs Using Convex Optimization

Giovanni De Micheli, David Atienza Alonso, Srinivasan Murali

The increasing processing capability of Multi-Processor Systems-on-Chips (MPSoCs) is leading to an increase in chip power dissipation, which in turn leads to significant increase in chip temperature. An important challenge facing the MPSoC designers is to ...

2007

Continuous Bytecode Instruction Counting for CPU Consumption Estimation

Andrea Camesi

As an execution platform, the Java Virtual Machine (JVM) provides many benefits in terms of portability and security. However, this advantage turns into an obstacle when it comes to determining the computing resources (CPU, memory) a program will require t ...

IEEE Computer Society Press2006

Processeur à haut degré de parallélisme basé sur des composantes sérielles

Ralph Hoffmann

Nowaday, the world of processors is still dominated by the RISC architectures, which foundations have been laid down in the 70's. The RISC concept may be summarized by one word : simplicity. With this concept, much simpler architectures are born, in partic ...

EPFL2004