Publications associées à A Hybrid CDAC-Threshold Configuring SAR ADC in 28nm FDSOI CMOS

An Ultralow-Power Triaxial MEMS Accelerometer With High-Voltage Biasing and Electrostatic Mismatch Compensation

This article presents a triaxial micro electromechani-cal system (MEMS) capacitive accelerometer using a high-voltage biasing technique to achieve high resolution with ultralow power. The accelerometer system generates a differential pair of high voltages ...

Ieee-Inst Electrical Electronics Engineers Inc2024

Cascaded all-optical quantization employing step-size MMI and shape-optimized power splitter

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As a key unit of future high-throughput communications, optical analog to digital converter (OADC) with all-optical quantizer element that simultaneously possesses high resolution, large bandwidth and compact size is highly promising. A pending issue of co ...

ELSEVIER SCI LTD2023

Digital One-Shot Charge-balancing Method for Implantable Current-Mode Electrical Stimulation

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A low-power digital charge balancing system, which ensures the safe operation of constant-current biphasic stimulation is presented. The concept of the proposed charge-balancing technique is to utilize a hybrid method consisting of anodic pulse modulation ...

IEEE2023

An Error-Based Approximation Sensing Circuit for Event-Triggered Low-Power Wearable Sensors

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Event-based sensors have the potential to optimize energy consumption at every stage in the signal processing pipeline, including data acquisition, transmission, processing, and storage. However, almost all state-of-the-art systems are still built upon th ...

2023

An All-Digital 1.25 Mbps 5-Subcarrier OFDM Backscatter Uplink with Delta-Sigma Modulation for Improved Spurious-Free Dynamic Range

James Daniel Rosenthal

This paper describes an all-digital backscatter modulation approach leveraging delta-sigma modulation (DSM) to improve the in-channel spectral characteristics of orthogonal frequency division multiplexed (OFDM) backscatter communication. We demonstrate thr ...

IEEE2022

Spike-Based Sensing and Communication for Highly Energy-Efficient Sensor Edge Nodes

Mihai Adrian Ionescu, Teodor Rosca

Highly energy-efficient wireless sensor nodes are a prerequisite for a sustainable operation of the Internet of things. Therefore, classical approaches for system design based on digital signal processing are not a viable solution, but system design has to ...

IEEE2022

An Energy-Efficient Bridge-to-Digital Converter for Implantable Pressure Monitoring Systems

Marco Mattavelli, Catherine Dehollain, Diego Ruben Barrettino, Franco Maloberti, Kerim Türe, Mustafa Besirli

This paper presents an energy-efficient, duty-cycled, and spinning excitation bridge-to-digital converter (BDC) designed for implantable pressure sensing systems. The circuit provides the measure of the pulmonary artery pressure that is particularly releva ...

2022

High-Speed ADC Design and Optimization for Wireline Links

Ayça Akkaya

The ever-growing global internet traffic has increased demand for higher speed data transmission. As the bandwidth requirements of wireline links increase, extensive digital equalization techniques are required to compensate for the high-frequency channel ...

EPFL2021

Energy-Efficient Design Techniques for High-Speed Wireline Serial Links

Firat Çelik

The exponential growth in computing power and multimedia services has caused a tremendous increase in data traffic in recent years. This increase in data traffic brings a strong demand for data bandwidth of electrical input/output (I/O) links and pushes th ...

EPFL2021

An 8-Bit 800 MS/s Loop-Unrolled SAR ADC With Common-Mode Adaptive Background Offset Calibration in 28 nm FDSOI

Yusuf Leblebici, Ayça Akkaya, Firat Çelik

This paper presents a low-power single-channel 8-bit loop-unrolled (LU) successive approximation register (SAR) analog-to-digital-converter (ADC) with a novel common-mode adaptive background comparator offset calibration scheme. LU-SAR ADCs use multiple co ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Modified Joint Channel-and-Data Estimation for One-Bit Massive MIMO

Saeed Saadatnejad, Mohammadhossein Bahari, Mahdi Amiri

Centralized and cloud computing-based network architectures are the promising tracks of future communication systems where a large scale compute power can be virtualized for various algorithms. These architectures rely on high-performance communication lin ...

IEEE2021

On the 2D Post-Processing of Brillouin Optical Time-Domain Analysis

Luc Thévenaz, Simon Adrien Zaslawski, Zhisheng Yang

The benefits and limitations inherent to the 2D post-processing of measurements from Brillouin optical time-domain analyzers are investigated from a fundamental point of view. In a preliminary step, the impact of curve fitting on the precision of the estim ...

IEEE Institute of Electrical and Electronics Engineers2020

High Speed SAR ADC Architectures in 28nm FDSOI CMOS

Mustafa Kilic

The demand on high speed Analog to Digital Converters (ADCs) has increased considerably the last years. From communications circuit to high speed oscilloscopes, Giga Samples per second (GS/s) ADCs are requested. With the scaling of the CMOS technology, des ...

EPFL2019

Analysis of photosensor frontends for biomedical applications: a focus on noise

Paul Stanislas Gosselin

Photosensing has proven to be highly useful in biomedical research and medical care. Being able to detect and quantify the light emitted by fluorescent or bioluminescent reporters has significantly participated in the development of new cancer treatments a ...

EPFL2019

A CMOS Analog Front-End for Implantable Pulmonary Artery Pressure Monitoring System

Marco Mattavelli, Catherine Dehollain, Diego Ruben Barrettino, Kerim Türe, Mustafa Besirli

This paper presents an energy-efficient analog front-end circuit to monitor the pulmonary artery pressure (PAP) with piezoresistive pressure sensors. A low-power capacitively-coupled instrumentation amplifier (CCIA) is developed in order to boost the ampli ...

IEEE2019

Design Techniques for Ultra High Frequency Clock Generation in 28 nm FDSOI Technology

Hasene Gülperi Özsema

Twentieth century has been the golden age of semiconductor industry by achieving a high level of growth as a courtesy of developments in fabrication techniques and downscaling of the technology. Since the downscaling in current lithography technology is re ...

EPFL2017

A DAC Assisted Speed Enhancement Technique for High Resolution SAR ADC

Yusuf Leblebici, Mustafa Kilic

In this paper, a technique aiming at enhancing the conversion speed of asynchronous high resolution SAR ADCs is presented. In conventional SAR ADCs, the capacitive DAC size is growing exponentially with the converter resolution. The settling time of the MS ...

2017

Pump-linewidth-tolerant wavelength multicasting using soliton Kerr frequency combs

Tobias Kippenberg, Martin Hubert Peter Pfeiffer, Amirhossein Mohajerin Ariaei, Arne Kordts, Maxim Karpov, Lin Zhang

We experimentally demonstrate pump-linewidth-tolerant wavelength multicasting using microresonator-based soliton Kerr frequency combs. When Kerr comb lines serve as coherent pumps in a periodically poled lithium niobate waveguide, the linewidth of the mult ...

Optical Soc Amer2017

A reconfigurable cryogenic platform for the classical control of quantum processors

Edoardo Charbon, Fabio Sebastiano, Harald Arjan Robert Homulle

The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the hea ...

2017

A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications

Edoardo Charbon, Harald Arjan Robert Homulle

We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmw ...

2016