Hardware/Software Co-Design and Reliability Analysis of Ultra-Low Power Biomedical Devices

Smart health monitoring devices, known as Wireless Body Sensor Nodes (WBSN) are transforming today's health-care landscape, shifting it from traditional hospital-based methods toward more personalized approaches. Their demand is ever-increasing in the modern world, where an overwhelming majority of deaths are caused by chronic cardiovascular diseases. WBSNs provide low-cost, unobtrusive and wearable solutions for continuous health-monitoring. These small autonomous devices are capable of acquiring, processing and wirelessly transmitting biological signals to medical personnel, typically relying on a limited on-board power source. Since WBSNs are desired to operate over prolonged periods, producing potentially critical data, their reliability and energy efficiency are of paramount importance. State-of-the-Art (SoA) WBSNs are able to process on-board the sensed bio-signals, like Electrocardiograms (ECG), transmitting only compact sets of clinically-relevant features instead of the entire acquired signal. This scenario moves the energy bottleneck of such devices from the transmission link to the computation-intensive Bio-Signal Processing (BSP) segment. To improve their energy efficiency, in this thesis, I propose strategies ranging from architectural to technology levels. First, I explore the applicability of a relaxed-reliability computing paradigm resulting from ultra-low voltage operations. I begin by modeling memory failures ensuing from voltage over-scaling and fabrication variability-related issues, studying their effects at the application level. To this end, I introduce novel data significance-based protection approaches for countering failures in embedded memories, showcasing up to 20% reduction in the energy budget compared to existing solutions. In addition, I devise lightweight hardware- and software-level error monitoring solutions that cope with memory failures, when unprotected. Experimental results demonstrate that these strategies ensure minimal performance degradation, achieving up to 24% energy savings with respect to the SoA. In the second part of the thesis, I employ novel approaches featuring heterogeneous WBSNs with a reconfigurable accelerator and emerging memory technologies. I commence by performing a study to identify the computationally intensive segments of BSP algorithms that can potentially be accelerated on a reconfigurable fabric. I adopt a top-down approach to do so, extracting kernels from the high-level application code, eventually optimizing and mapping them for execution on a time- and resource-shared Coarse Grain Reconfigurable Array (CGRA). I prove the effectiveness of the proposed platform by exhibiting up to 11x performance improvement and 37% energy savings over the SoA. Then, I combine relaxed-reliability computation and CGRA-based WBSNs, with my experiments exhibiting as much as 70% reduction in energy consumption compared to the current SoA, while assuring safe system operation. I conclude this work b