Power-Performance Scalable Integrated Circuit Design Using Subthreshold MOS

The potentials of subthreshold metal-oxide-semiconductor (MOS) solid-state devices for implementing widely adjustable performance integrated circuits with very low power consumption have been investigated. The main concentration of this work is developing some techniques for implementing power-frequency scalable mixed-mode circuits. To implement ultra-low-power digital circuits, subthreshold source-coupled logic (STSCL) topology is proposed. It is shown that this topology can be used in a very wide operating frequency range with a high power efficiency. The STSCL family can be utilized for implementing ultra-low-power circuits where the power consumption of conventional static CMOS circuits is limited by the channel subthreshold residual (leakage) current. Some reliable design techniques for implementing STSCL circuits in very low bias current levels have been developed. Using the proposed techniques, some basic building blocks as well as more complex test structures have been implemented and tested. Meanwhile, some techniques such as stacking, pipelining and output buffering have been introduced to improve the performance of this type of circuits in terms of speed of operation and power consumption. In order to construct complex digital systems based on this topology, two standard cell libraries have been developed containing different types of STSCL gates with different driving strengths. This library also includes static random access memory (SRAM) cells. Experimental results show that the stand-by (leakage) current consumption of the STSCL memory cells is well below their CMOS counterparts. To control the speed of operation in the proposed STSCL circuits, a very wide tuning range phase-locked loop (PLL) circuit has been designed and implemented. To achieve the required adjustability range, an adaptive bandwidth PLL benefitting self-bias technique has been introduced. In addition, the exponential I-V characteristics of subthreshold MOS devices have been exploited for implementing widely adjustable performance analog integrated circuits. Two new approaches for implementing widely tunable and power-efficient continuous-time filters are developed. A MOSFET-C filter with very low cutoff frequency using a novel high-valued oating resistance, and a wide-tuning range transconductance-C filter using a linearized biquadratic topology have been introduced. The possibility of implementing reconfigurable analog-to-digital converters (ADCs) has been also studied. Two different scalable ADCs based on folding and interpolating and ΣΔ topologies have been implemented. The proposed filters in addition to the proposed frequency-power scalable ADC data converters can be used to construct a power-efficient and widely adjustable operating frequency analog front end. The main concepts proposed in this work have been supported by extensive analysis and measurement results.