Publication

Low noise, low power front end electronics for pixelized TFA sensors

Christophe Ballif, Matthieu Despeisse
2009
Conference Papers

Résumé

Thin Film on ASIC (TFA) technology combines advantages of two commonly used pixel imaging detectors, namely, Monolithic Active Pixels (MAPs) and Hybrid Pixel detectors. Thanks to direct deposition of a hydrogenated amorphous silicon (a- Si:H) sensor lm on top of the readout ASIC, TFA shows the similarity to MAP imagers, allowing, however, more sophisticated front–end circuitry to extract the signals, like in case of Hybrid Pixel technology. In this paper we present preliminary experimental results of TFA structures, obtained with 10 μm thick hydrogenated amorphous silicon sensors, deposited directly on top of integrated circuit optimized for tracking applications at linear collider experiments. The signal charges delivered by such a-Si:H n-i-p diode are small; about 37 e-/μm for minimum ionizing particles, therefore a low noise, high gain and very low power of the front- end are of primary importance. The developed demonstrator chip, designed in 250 nm CMOS technology, comprises an array of 64 by 64 pixels laid out in 40 μm by 40 μm pitch.

Source officielle

https://infoscience.epfl.ch/entities/publication/6fb441a0-43fe-4bad-9dc8-cbc0dc454642

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Christophe Ballif, Matthieu Despeisse
2009
Conference Papers

Résumé

Source officielle

https://infoscience.epfl.ch/entities/publication/6fb441a0-43fe-4bad-9dc8-cbc0dc454642

À propos de ce résultat

Concepts associés (32)

Active-pixel sensor

An active-pixel sensor (APS) is an , which was invented by Peter J.W. Noble in 1968, where each pixel sensor unit cell has a photodetector (typically a pinned photodiode) and one or more active transistors. In a metal–oxide–semiconductor (MOS) active-pixel sensor, MOS field-effect transistors (MOSFETs) are used as amplifiers. There are different types of APS, including the early NMOS APS and the now much more common complementary MOS (CMOS) APS, also known as the CMOS sensor.

Three-dimensional integrated circuit

A three-dimensional integrated circuit (3D IC) is a MOS (metal-oxide semiconductor) integrated circuit (IC) manufactured by stacking as many as 16 or more ICs and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or Cu-Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. The 3D IC is one of several 3D integration schemes that exploit the z-direction to achieve electrical performance benefits in microelectronics and nanoelectronics.

Complementary metal oxide semi-conductor

vignette|Vue en coupe d'un transistor MOS On appelle CMOS, ou Complementary Metal Oxide Semiconductor, une technologie de fabrication de composants électroniques et, par extension, les composants fabriqués selon cette technologie. Ce sont pour la plupart des circuits logiques (NAND, NOR) comme ceux de la famille Transistor-Transistor logic (TTL) mais, à la différence de ces derniers, ils peuvent être aussi utilisés comme résistance variable.

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