A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration

In this work, a chip-level post-CMOS processing protocol for 3D integration is presented to achieve multilayer stacking. This protocol includes TSV formation on the top chip, bonding the chips on top of each other, and finally the electrical connection processes. Homogeneous CMOS chips with different thicknesses are utilized to optimize the process flow. The first electrical measurements are obtained from dummy chips composed of serially connected TSV interconnects fabricated using this process flow. As a result, an average resistance value of a single TSV is calculated as 180 mΩ for current values of up to 100 mA.