An Experimental Study of Heterostructure Tunnel FET Nanowire Arrays: Digital and Analog Figures of Merit from 300K to 10K

In this work, we experimentally report the figures of merit of state-of-the-art heterostructure Tunnel Field-Effect-Transistor (TFET) arrays from room (300K) down to cryogenic temperature (10K) at supply voltages below 400mV. We demonstrate here, for the first time, that InAs/InGaAsSb/GaSb Nanowire (NW) TFETs are robust enough to maintain excellent figures of merit over a large temperature range even in devices with a large number arrayed nanowires (here, from 4 to 184 nanowires per device), accounting for technological variability. The investigated Tunnel FETs have temperature-independent min and average subthreshold swings of 45mV/dec/67mV/dec in large NW arrays, versus similar to 36/45mV/dec in smaller arrays, once the trap-assisted tunneling is removed (from 150K down to 10K). In all NW arrays we observe improvement of the on-current and of maximum transconductance, g(max), at cryogenic temperatures, with very little dependence of temperature, from 150K to 10K. The paper reports that in the range 150K to 10K only band-to-band-tunneling dominates the analog figures of merit of Tunnel FETs; we measured transconductance efficiencincies higher than 60V(-1) for small arrays (breaking the limit of CMOS at RT) and close to 42V(-1) for large arrays, for supply volrages smaller than 100mV, offering the possibility to design future energy efficient readouts and analog-to-digital converters. In contrast with cryogenic MOSFETs, Tunnel FETs show almost no hysteresis (