Publications associées à Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link

A 0.14-nJ/b 200-Mb/s 2.7-3.5-GHz Quasi-Balanced FSK Transceiver With PLL-Based Modulation and Sideband Energy Detection

This paper describes a balanced frequency shift keying (FSK) modulation, namely quasi-balanced FSK (QB-FSK), for energy-efficient high-data-rate communication. Not suffering from data-pattern dependency, the proposed modulation method enables frequency mod ...

2024

Automated Design Appraisal: Estimating Real Estate Price Growth and Value at Risk Due to Local Development

Adam Robert Swietek

Financial criteria in architectural design evaluation are limited to cost performance. Here, I introduce a method – Automated Design Appraisal (ADA) – to predict the market price of a generated building design concept within a local urban context. Integrat ...

2023

Energy-Efficient Design Techniques for High-Speed Wireline Serial Links

Firat Çelik

The exponential growth in computing power and multimedia services has caused a tremendous increase in data traffic in recent years. This increase in data traffic brings a strong demand for data bandwidth of electrical input/output (I/O) links and pushes th ...

EPFL2021

Time-Varying Components for Enhancing Wireless Transfer of Power and Information

Romain Christophe Rémy Fleury, Mohammad Sajjad Mirmoosa, Xuchen Wang

Temporal modulation of components of electromagnetic systems provides an exceptional opportunity to engineer the response of those systems in a desired fashion, both in the time and frequency domains. For engineering time-modulated systems, one needs to th ...

American Physical Society (APS)2021

High-Speed ADC Design and Optimization for Wireline Links

Ayça Akkaya

The ever-growing global internet traffic has increased demand for higher speed data transmission. As the bandwidth requirements of wireline links increase, extensive digital equalization techniques are required to compensate for the high-frequency channel ...

EPFL2021

Resource Trade-Offs in Circuits and Systems: from Neurotechnology to Communications

Arda Uran

This thesis aims to explore and exploit trade-offs in integrated circuits and systems to overcome the fundamental bottlenecks faced by future data acquisition and communication systems. Specifically, we target the emerging implantable neurotechnology and t ...

EPFL2021

Demonstration of Tunable Optical Aggregation of QPSK to 16-QAM Over Optically Generated Nyquist Pulse Trains Using Nonlinear Wave Mixing and a Kerr Frequency Comb

Tobias Kippenberg, Martin Hubert Peter Pfeiffer, Fatemeh Alishahi, Arne Kordts, Maxim Karpov, Ahmad Fallahpour, Cong Liu

A tunable and reconfigurable optical aggregation system is experimentally demonstrated. Optical Nyquist pulses are generated on multiple channels using a microresonator-based Kerr optical frequency comb and insertion of uniform lines by an intensity modula ...

IEEE Institute of Electrical and Electronics Engineers2020

High Precision Capacitive Moisture Sensor for Polymers: Modeling and Experiments

Marco Mattavelli, Jean-Michel Sallese, Catherine Dehollain, Diego Ruben Barrettino

In this work a high precision capacitive moisture sensor for polymers was designed and fabricated. The device is part of a compact, fast, and economic moisture analyzer capable of reaching a similar precision than commercial moisture analyzers based on the ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Yusuf Leblebici, Alessandro Cevrero, Andreas Peter Burg, Gain Kim, Lukas Kull, Thomas Toifl, Cosimo Aprile, Ilter Ozkaya

This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates a fully digital equalization data-path, with a synthesized and automatically placed a ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Physical Layer Aspects of LoRa and Full-Duplex Wireless Transceivers

Orion Afisiadis

Wireless communications are currently faced with two main challenges. The first challenge stems from the enormous number of Internet of Things (IoT) devices that transmit very small amounts of data. The second challenge is the need for ever-increasing data ...

EPFL2020

ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links

Yusuf Leblebici, Seyed Armin Tajalli, Ayça Akkaya, Firat Çelik

This paper presents a comparative study, analyzing the potentials of pulse amplitude modulation (PAM) for implementing next generation high-speed copper wireline links. This comparative study analyzes the sensitivities of PAM2, PAM4 and PAM8 to inter-symbo ...

IEEE2019

A 4.8pJ/b 6Gb/s ADC-Based PAM-4 Wireline Receiver Data -Path with Cyclic Prefix in 14nm FinFET

Yusuf Leblebici, Alessandro Cevrero, Andreas Peter Burg, Gain Kim, Lukas Kull, Thomas Toifl, Cosimo Aprile, Ilter Ozkaya

This work presents an ADC-bascd receiver (RX) data-path for frame-based PAM-4 modulation with a cyclic prefix (CP). Similar to discrete multi-tone (DMT) modulation, a frame of PAM-4 symbols arc protected from the channel delay spread by the CP taps. A PAM- ...

IEEE2019

Demonstration of Tunable and Reconfigurable Optical Nyquist Channel Aggregation of QPSK-to-16QAM and BPSK-to-4PAM Using Nonlinear Wave Mixing and a Kerr Frequency Comb

Tobias Kippenberg, Martin Hubert Peter Pfeiffer, Yiming Cao, Fatemeh Alishahi, Arne Kordts, Maxim Karpov, Ahmad Fallahpour

A tunable and reconfigurable optical Nyquist channels aggregation is experimentally demonstrated. The proposed method two aggregate lower order modulation formats into a single higher order one. Two 16 Gbaud QPSK Nyquist pulses aggregated to a 16 QAM Nyqui ...

IEEE2019

Lora Digital Receiver Analysis And Implementation

Andreas Peter Burg, Matthieu Cotting, Orion Afisiadis, Reza Ghanaatian Jahromi

Low power wide area network technologies (LPWANs) are attracting attention because they fulfill the need for long range low power communication for the Internet of Things. LoRa is one of the proprietary LPWAN physical layer (PHY) technologies, which provid ...

IEEE2019

Experimental demonstration of three-fold wavelength multicasting of a 64-QAM 120 Gbit/s data channel using a Kerr frequency comb and nonlinear wave mixing

Tobias Kippenberg, Martin Hubert Peter Pfeiffer, Fatemeh Alishahi, Arne Kordts, Maxim Karpov, Ahmad Fallahpour

We experimentally demonstrate three-fold wavelength multicasting of a 64-quadrature-amplitude-modulation (QAM), 120-Gbit/s data channel using a microresonator Kerr frequency comb and nonlinear wave mixing. The multicasting is achieved with a data signal an ...

SPIE-INT SOC OPTICAL ENGINEERING2019

JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS

Yusuf Leblebici, Seyed Armin Tajalli, Andreas Peter Burg, Ayça Akkaya, Firat Çelik

JESD204B compliant low-voltage differential signaling (LVDS), and source-series-terminated (SST) transmitters in 28 nm FD-SOI CMOS technology are presented with 1.1 pJ/bit and 1.7 pJ/bit at 12.5 Gb/s, respectively. An external 6.25 GHz single-ended clock, ...

IEEE2019

Multi-Tone Signaling and ADC-Based Digital Receiver for High-Speed Wireline Serial Links

Gain Kim

The exponential growth of Internet traffic and related demands for higher communication speed pushes processor-to-processor and processor-to-memory interconnects to provide further higher data-rate. Often time, processor-to-memory interconnectsâ speed is ...

EPFL2018

Adaptive Receiver Design for High Speed Optical Communication

Ilter Ozkaya

Conventional input/output (IO) links consume power, independent of changes in the bandwidth demand by the system they are deployed in. As the system is designed to satisfy the peak bandwidth demand, most of the time the IO links are idle but still consumin ...

EPFL2018

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

Yusuf Leblebici, Alessandro Cevrero, Gain Kim, Lukas Kull, Thomas Toifl, Cosimo Aprile, Ilter Ozkaya

This paper presents a parallel implementation technique of digital equalizer for high-speed wireline serial link receiver (RX). In wireline RX, inter-symbol interference (ISI) is mitigated by continuous-time linear equalizer, and the remaining ISI is cance ...

2018

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders

Andreas Peter Burg, Lukas Kull, Thomas Toifl, Giovanni Cherubini

The implementation of a 25.6-Gb/s four-level pulse-amplitude-modulation (4-PAM) reduced-state sliding-block Viterbi detector (VD) is presented. The power consumption of the VD is 105 orilV at a supply voltage of 0.7 V, corresponding to an energy efficiency ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018