System and method for removing scalloping and tapering effects in high aspect ratio through-silicon vias of wafers

A method for manufacturing vias in a silicon wafer, the silicon wafer having a crystal orientation, and having a plane that is perpendicular to a surface of the wafer, tilted by 35.26°, the method comprising the steps of providing a mask having a rhomboidal-shaped opening onto a surface of the silicon wafer, such that edges of the rhomboidal-shaped opening line up with a plane of a crystalline structure of the silicon wafer, etching a hole in the silicon wafer at the rhomboidal-shaped opening, and polishing the hole after the etching by a anisotropic etching.