Publications associées à Exact Synthesis for Logic Synthesis Applications with Complex Constraints

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

EPFL2024

Algebraic and Boolean Methods for SFQ Superconducting Circuits

Giovanni De Micheli, Alessandro Tempia Calvino

Rapid single-flux quantum (RSFQ) is one of the most advanced and promising superconducting logic families, offering exceptional energy efficiency and speed. RSFQ technology requires delay registers (DFFs) and splitter cells to satisfy the path-balancing an ...

2024

Scalable Logic Rewriting Using Don’t Cares

Giovanni De Micheli, Alessandro Tempia Calvino

Logic rewriting is a powerful optimization technique that replaces small sections of a Boolean network with better implementations. Typically, exact synthesis is used to compute optimum replacement on-the-fly, with possible support for Boolean don't cares. ...

2024

Strain relaxation and multidentate anchoring in n-type perovskite transistors and logic circuits

Mohammad Khaja Nazeeruddin, Olga Syzgantseva

The engineering of tin halide perovskites has led to the development of p-type transistors with field-effect mobilities of over 70 cm2 V-1 s-1. However, due to their background hole doping, these perovskites are not suitable for n-type transistors. Ambipol ...

Nature Portfolio2024

Improving Standard-Cell Design Flow using Factored Form Optimization

Giovanni De Micheli, Alessandro Tempia Calvino

Factored form is a powerful multi-level representation of a Boolean function that readily translates into an implementation of the function in CMOS technology. In particular, the number of literals in a factored form correlates strongly with the number of ...

IEEE2023

Technology Mapping Using Multi-output Library Cells

Giovanni De Micheli, Alessandro Tempia Calvino

Technology mapping transforms a technology-independent representation into a technology-dependent one given a library of cells. Even if technology libraries contain multi-output cells, state-of-the-art techniques fully exploit single-output cells only. Mul ...

2023

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Stefan Nikolic

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

EPFL2023

Unraveling the Electrochemical Electrode Coupling in Integrated Organic Electrochemical Transistors

Hsin Tseng, Matteo Cucchi

Organic electrochemical transistors (OECTs) have gained enormous attention due to their potential for bioelectronics and neuromorphic computing. However, their implementation into real-world applications is still impeded by a lack of understanding of the c ...

WILEY-V C H VERLAG GMBH2023

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition

Giovanni De Micheli, Andrea Costamagna

Approximate logic synthesis is an emerging field that tolerates errors in the synthesized logic circuits for better optimization quality. Indeed, in many computing problems, the requirement of preserving the exact functionality either results in unnecessar ...

IEEE2022

Utilizing XMG-based Synthesis to Preserve Self-Duality for RFET-Based Circuits

Giovanni De Micheli, Heinz Riener, Alessandro Tempia Calvino, Shubham Rai, Akash Kumar

Individual transistors based on emerging reconfigurable nanotechnologies exhibit electrical conduction for both types of charge carriers. These transistors (referred to as Reconfigurable Field-Effect Transistors (RFETs)) enable dynamic reconfiguration to d ...

2022

From C/C plus plus Code to High-Performance Dataflow Circuits

Paolo Ienne, Lana Josipovic, Andrea Guerrieri

High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis

Paolo Ienne, Lana Josipovic

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Unleashing Parallelism in Elastic Circuits with Faster Token Delivery

Paolo Ienne, Lana Josipovic, Andrea Guerrieri, Ayatallah Ahmed Gamal Kamal Elakhras

High-level synthesis (HLS) is the process of automatically generating circuits out of high-level language descriptions. Previous research has shown that dynamically scheduled HLS through elastic circuit generation is successful at exploiting parallelism in ...

IEEE COMPUTER SOC2022

Electronic transport in graphene nanoribbon junctions

Kristians Cernevics

Graphene nanoribbons (GNRs) - one-dimensional strips of graphene - share many of the exciting properties of graphene, such as ballistic transport over micron dimensions, strength and flexibility, but more importantly, they exhibit a tunable band gap that d ...

EPFL2022

Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies

Giovanni De Micheli, Heinz Riener, Shubham Rai, Akash Kumar

Emerging reconfigurable nanotechnologies allow the implementation of self-dual functions with a fewer number of transistors as compared to traditional CMOS technologies. To achieve better area results for Reconfigurable Field-Effect Transistors (RFET)-base ...

IEEE2021

Three-Input Gates for Logic Synthesis

Giovanni De Micheli, Eleonora Testa, Mathias Soeken, Dewmini Sudara Marakkalage, Heinz Riener

Most logic synthesis algorithms work on graph representations of logic functions with nodes associated with arbitrary logic expressions or simple logic functions and iteratively optimize such graphs. While recent multilevel logic synthesis efforts focused ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits

Giovanni De Micheli, Eleonora Testa, Heinz Riener, Siang-Yun Lee

Adiabatic quantum-flux-parametron (AQFP) circuits are a family of superconducting electronic (SCE) circuits that have recently gained growing interest due to their low-energy consumption, and may serve as alternative technology to overcome the down-scaling ...

IEEE2021

From Boolean functions to quantum circuits: A scalable quantum compilation flow in C++

Giovanni De Micheli, Giulia Meuli, Bruno Schmitt Antunes, Heinz Riener, Fereshte Mozafari Ghoraba

We propose a flow for automated quantum compila- tion. Our flow takes a Boolean function implemented in Python as input and translates it into a format appropriate for reversible logic synthesis. We focus on two quantum compilation tasks: uniform state pre ...

2021

High-Level Synthesis of Dynamically Scheduled Circuits

Lana Josipovic

High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. These tools almost universally build datapaths that are controlled using a centralized controller which relies on a static, compile-time schedule to determine ...

EPFL2021

Low-Latency High-Bandwidth Circuit and System Design for Trigger Systems in High Energy Physics

Marcos Vinícius Silva Oliveira

The increasing luminosity in HEP (High Energy Physics) colliders demands trigger systems to be more selective. First, more information from the detector is routed to the trigger system. Second, larger parts of this information are processed together. These ...

EPFL2021