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Related lectures (31)

Covers the basic principles and architecture of Field Programmable Gate Arrays (FPGAs) and their implementation options for digital circuits.

Programmable Logic Devices: PAL, GAL, CPLD

Covers PAL, GAL, CPLD, and the transition to FPGAs using HDLs.

FPGA Architecture: LUT and Routing Arrays

Explores FPGA architecture, including LUTs and routing arrays, scalability, and placement challenges.

Semicustom RTL Design: Design Flow and Standard Cells

Explores the RTL design flow, chip-level integration, standard cells, and static timing analysis in VLSI design.

Programmable Logic Devices: PAL, GAL, CPLD

Covers PAL, GAL, CPLD, and the evolution to FPGAs, explaining their architecture and advantages.

Hardware Description Languages

Explores the history and significance of Hardware Description Languages in automating design processes and describing parallel hardware.

FPGA Programming with Speedgoat: Real-Time Signal Processing

Focuses on implementing a square function generator using Speedgoat FPGA technology and real-time signal processing techniques.

Simulation-Based Verification

Explores simulation-based verification in VLSI systems using compiled-code and event-driven algorithms.

Logic Design: Basic Rules and Shannon's Expansion

Covers basic rules of logic design and Shannon's expansion in Boolean functions.

Semicustom RTL Design: Frontend with Synthesis

Covers the fundamentals of VLSI design, focusing on the semi-custom design flow.

Semicustom RTL Design: Backend

Explores the backend design flow in semicustom ASIC design, covering layout, clock tree generation, and tapeout preparation.

Molecular Transistors: Design and Simulation

Explores molecular transistors for logic computation, design, simulation, and fabrication, emphasizing interconnect parasitics and device performance.

Programmable Logic Devices: Introduction to GAL and CPLD

Introduces GAL and CPLD, covering PAL evolution, GAL limitations, and CPLD architecture.

How we design chips: The Digital VLSI Design Flow

Explores the principles and methodologies for designing integrated circuits, covering design flows, VLSI styles, abstraction levels, and the semiconductor ecosystem.

High-Level Synthesis: Formally Verified Elastic Circuits

Presents the development of a verified high-level synthesis compiler for elastic circuits.

Generating a CLK Generator (PLL) IP in Vivado

Covers the process of generating a Clock Generator (PLL) IP in Vivado using the Clocking Wizard tool.

Digital Design: Lowerbounds and Recommendations

Covers abstraction levels, EPFL design flow, lowerbounds, and layout recommendations.

Programmable Logic Circuits, FPGA

Explores logic circuit classification, FPGA design methodology, implementation, and Altera Cyclone IV architecture.

FPGA Programming with Speedgoat: A Comprehensive Overview

Covers FPGA programming with Speedgoat, focusing on synthesis, design practices, and practical examples.

In-System Debug and Custom AXI IP

Covers in-system debug, marking nets, generating debug IP, and reading from a custom AXI IP.

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