Publications related to Pentium II

Beam test performance of a prototype module with Short Strip ASICs for the CMS HL-LHC tracker upgrade

Qian Wang, Simone Scarfì, Varun Sharma, Konstantin Androsov, Xin Chen, Rakesh Chawla, Tian Cheng, Werner Lustermann, Andromachi Tsirou, Andrea Rizzi, Jessica Prisciandaro, David Vannerom, Davide Di Croce, Albert Perez, Alessandro Caratelli, François Robert, Davide Ceresa, Chun Xia, Yong Yang, Ajay Kumar, Ashish Sharma, Georgios Anagnostou, Muhammad Ahmad, Francesco Fiori, Kai Yi, Jing Li, Hui Wang, Stefano Michelis, François Bianchi, David Parker

The Short Strip ASIC (SSA) is one of the four front-end chips designed for the upgrade of the CMS Outer Tracker for the High Luminosity LHC. Together with the Macro-Pixel ASIC (MPA) it will instrument modules containing a strip and a macro-pixel sensor sta ...

2022

High-Performance III-V MOSFETs and Tunnel-FETs Integrated on Silicon

Clarissa Convertino

Silicon transistor scaling is approaching its end and a transition to novel materials and device concepts is more than ever essential. High-mobility compound semiconductors are considered promising candidates to replace silicon, targeting low-power logic a ...

EPFL2020

High Speed SAR ADC Architectures in 28nm FDSOI CMOS

Mustafa Kilic

The demand on high speed Analog to Digital Converters (ADCs) has increased considerably the last years. From communications circuit to high speed oscilloscopes, Giga Samples per second (GS/s) ADCs are requested. With the scaling of the CMOS technology, des ...

EPFL2019

High-Voltage Tolerant Bi-State Self-Biasing Output Driver using Cascade Complementary Latches in Twin-well CMOS Technology

Scott Anthony Lindner

The design of a bi-state output buffer that can handle 5 times the supply voltage is presented. The use of self-biasing stacked devices driven by a cascade of complementary latches allows all devices to operate within the limits set by the technology, thus ...

Ieee2016

Impact of body biasing on the retention time of gain-cell memories

Andreas Peter Burg, Adam Shmuel Teman, Pascal Andreas Meinerzhagen

Gain-cell-based embedded dynamic random-access memory (DRAMs) are a potential high-density alternative to mainstream static random-access memory (SRAM). However, the limited data retention time of these dynamic bitcells results in the need for power-consum ...

2013

One Joule per GFlop for BLAS2 Now!

Vincent Keller

Energy consumption is today one of the major topics that the HPC community tries to tackle. In this paper, the authors present a thought experiment aiming at building a node of a supercomputer based on a GPU (Nvidia GTX280). The paper concentrate on BLAS2 ...

American Institute of Physics2010

Performance and Energy Trade-offs Analysis of L2 on-Chip Cache Architectures for Embedded MPSoCs

Martino Ruggiero, Mohamed Mostafa Sabry Aly, Pablo Garcia del Valle

On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multi-processor systems. Following the trend set by high-performance processors, high-end embedded cores are moving from single-level on chip ...

2010

Macro-to-Microchannel Transition in Two-Phase Flow and Evaporation

Chin Lee Ong

Continuous development of highly efficient and compact cooling elements are driven by extensive developments of Micro-Electro-Mechanical Systems (MEMS) devices such as microprocessors or micro high-powered laser systems. As microprocessors continue to head ...

EPFL2010

Low noise, low power front end electronics for pixelized TFA sensors

Christophe Ballif, Matthieu Despeisse

Thin Film on ASIC (TFA) technology combines advantages of two commonly used pixel imaging detectors, namely, Monolithic Active Pixels (MAPs) and Hybrid Pixel detectors. Thanks to direct deposition of a hydrogenated amorphous silicon (a- Si:H) sensor lm on ...

2009

Ultra Low Power Subthreshold MOS Current Mode Logic Circuits Using a Novel Load Device Concept

Seyed Armin Tajalli, Eric Vittoz, Yusuf Leblebici

This article presents a novel and robust approach for implementing ultra-low power MOS current mode logic (MCML) circuits. To operate at very low bias currents, a simple and compact high resistance load device has been introduced. Operating in subthreshold ...

2007

Ultra low power subthreshold current-mode logic utilizing a novel PMOS load device

Seyed Armin Tajalli, Eric Vittoz, Yusuf Leblebici

A novel approach for implementing MOS current-mode logic (MCML) circuits that can operate with ultra low bias currents is introduced. Measurements of test structures fabricated in 0.18 μm CMOS technology show that the proposed PMOS load device concept can ...

2007

SOI mixed-mode design techniques and case studies

Marija Blagojevic

Since the emergence of Silicon On Insulator (SOI) technology the research activities have been concentrated on a detailed analysis of SOI devices and their use in different application fields (low-voltage, low-power circuits, high temperature electronics, ...

EPFL2005