Publications related to Massively parallel processor array

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

Acceleration of graph pattern mining and applications to financial crime

Jovan Blanusa

Various forms of real-world data, such as social, financial, and biological networks, can be represented using graphs. An efficient method of analysing this type of data is to extract subgraph patterns, such as cliques, cycles, and motifs, from graphs. For ...

EPFL2023

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Aurélien François Gilbert Bloch

Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...

EPFL2023

DChannel: Accelerating Mobile ApplicationsWith Parallel High-bandwidth and Low-latency Channels

Haitham Al Hassanieh

Interactive mobile applications like web browsing and gaming are known to benefit significantly from low latency networking, as applications communicate with cloud servers and other users' devices. Emerging mobile channel standards have not met these needs ...

USENIX ASSOC2023

Decentralized in-order execution of a sequential task-based code for shared-memory architectures

Charly Nicolas Lucien Castes

The hardware complexity of modern machines makes the design of adequate programming models crucial for jointly ensuring performance, portability, and productivity in high-performance computing (HPC). Sequential task-based programming models paired with adv ...

IEEE COMPUTER SOC2022

Faster Parallel Training of Word Embeddings

Martin Jaggi

Word embeddings have gained increasing popularity in the recent years due to the Word2vec library and its extension fastText that uses subword information. In this paper, we aim at improving the execution speed of fastText training on homogeneous multi- an ...

IEEE COMPUTER SOC2021

Quantum ESPRESSO toward the exascale

Nicola Marzari, Iurii Timrov, Roberto Car, Andrea Ferretti

Quantum ESPRESSO is an open-source distribution of computer codes for quantum-mechanical materials modeling, based on density-functional theory, pseudopotentials, and plane waves, and renowned for its performance on a wide range of hardware architectures, ...

AMER INST PHYSICS2020

An Optimizing Multi-platform Source-to-source Compiler Framework for the NEURON MODeling Language

Felix Schürmann, James Gonzalo King, Michael Lee Hines, Pramod Shivaji Kumbhar, Omar Awile, Jorge Blanco Alonso, Liam Roger George Keegan

Domain-specific languages (DSLs) play an increasingly important role in the generation of high performing software. They allow the user to exploit domain knowledge for the generation of more efficient code on target architectures. Here, we describe a new c ...

Springer2020

On Linear Learning with Manycore Processors

Martin Jaggi

A new generation of manycore processors is on the rise that offers dozens and more cores on a chip and, in a sense, fuses host processor and accelerator. In this paper we target the efficient training of generalized linear models on these machines. We prop ...

IEEE COMPUTER SOC2019

RPCValet: NI-Driven Tail-Aware Balancing of µs-Scale RPCs

Babak Falsafi, Alexandros Daglis, Mark Johnathon Sutherland

Modern online services come with stringent quality requirements in terms of response time tail latency. Because of their decomposition into fine-grained communicating software layers, a single user request fans out into a plethora of short, μs-scale RPCs, ...

ACM2019

Asynchronous Branch-Paralle Simulation of Detailed Neuron Models

Felix Schürmann, Michael Lee Hines

Simulations of electrical activity of networks of morphologically detailed neuron models allow for a better understanding of the brain. State-of-the-art simulations describe the dynamics of ionic currents and biochemical processes within branching topologi ...

2019

Phasor-based widefield FLIM using a gated 512×512 single-photon SPAD imager

Claudio Bruschini, Edoardo Charbon, Ivan Michel Antolovic, Arin Can Ülkü

Single-photon avalanche diode (SPAD) imagers can perform fast time-resolved imaging in a compact form factor, by exploiting the processing capability and speed of integrated CMOS electronics. Developments in SPAD imagers have recently made them compatible ...

2019

A Machine Learning-Based Strategy for Efficient Resource Management of Video Encoding on Heterogeneous MPSoCs

David Atienza Alonso, Marina Zapater Sancho, Arman Iranfar, William Andrew Simon

The design of new streaming systems is becoming a major area of research to deploy services targeted in the Internet-of-Things (IoT) era. In this context, the new High Efficiency Video Coding (HEVC) standard provides high efficiency and scalability of qual ...

2018

Improved Massively Parallel Computation Algorithms for MIS, Matching, and Vertex Cover

Slobodan Mitrovic, Mohsen Ghaffari

We present O(log log n)-round algorithms in the Massively Parallel Computation (MPC) model, with a(n) memory per machine, that compute a maximal independent set, a 1 + epsilon approximation of maximum matching, and a 2 + epsilon approximation of minimum ve ...

ASSOC COMPUTING MACHINERY2018

Massively parallel data processing for quantitative total flow imaging with optical coherence microscopy and tomography

Theo Lasser, Paul James Marchand, Daniel Pawel Szlag, Marcin Antoni Sylwestrzak

We present an application of massively parallel processing of quantitative flow measurements data acquired using spectral optical coherence microscopy (SOCM). The need for massive signal processing of these particular datasets has been a major hurdle for m ...

Elsevier2017

Elastic transactions

Rachid Guerraoui, Vincent Gramoli, Pascal Felber

This paper presents elastic transactions, an appealing alternative to traditional transactions, in particular to implement search structures in shared memory multicore architectures. Upon conflict detection, an elastic transaction might drop what it did so ...

Academic Press Inc Elsevier Science2017

Programming Models and Methods for Heterogeneous Parallel Embedded Systems

Marco Mattavelli, Simone Casale Brunet, Endri Bezati

The growing complexity of digital signal processing applications makes a compelling case for the adoption of higher-level programming models such as dataflow for the implementation of applications on programmable logic devices and many/multi-core embedded ...

2016

A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache

Giovanni De Micheli, Luca Benini

The use of multi-core clusters is a promising option for data-intensive embedded applications such as multi-modal sensor fusion, image understanding, mobile augmented reality. In this paper, we propose a power-efficient 3-D on-chip interconnect for multi-c ...

IEEE2016

Parallel Inverse Kinematics for Multithreaded Architectures

Ronan Boulic, Benoît Le Callennec, Mentar Mahmudi, Pawan Kumar Harish

In this article, we present a parallel prioritized Jacobian-based inverse kinematics algorithm for multithreaded architectures. We solve damped least squares inverse kinematics using a parallel line search by identifying and sampling critical input paramet ...

Association for Computing Machinery2016

HRL: Efficient and Flexible Reconfigurable Logic for Near-Data Processing

Christos Kozyrakis

The energy constraints due to the end of Dennard scaling, the popularity of in-memory analytics, and the advances in 3D integration technology have led to renewed interest in near-data processing (NDP) architectures that move processing closer to main memo ...

Ieee2016