Clock rate

Applied sciences
Computer engineering
Hardware engineering
Microprocessors

About
Privacy
Disclaimer

Graph Chatbot

Related publications (31)

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

Andrea Bonetti

As an increase of intelligent and self-powered devices is forecasted for our future everyday life, the implementation of energy-autonomous devices that can wirelessly communicate data from sensors is crucial. Even though techniques such as voltage scaling ...

EPFL2019

A 30-frames/s, 252 x 144 SPAD Flash LiDAR With 1728 Dual-Clock 48.8-ps TDCs, and Pixel-Wise Integrated Histogramming

Edoardo Charbon, Ivan Michel Antolovic, Scott Anthony Lindner, Chunmin Zhang, Juan Mata Pavia, Martin Wolf

A 252 x 144 single-photon avalanche diode (SPAD) pixel sensor, called Ocelot, is reported for light detection and ranging (LiDAR). The sensor, fabricated in the 180-nm CMOS technology, features 1728 12-bit time-to-digital converters (TDCs) with 48.8-ps res ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

A 6.5-GHz Cryogenic All-Pass Filter Circulator in 40-nm CMOS for Quantum Computing Applications

Edoardo Charbon, Andrea Ruffino, Yatao Peng, Fabio Sebastiano

Cryogenic solid-state quantum processors require classical control and readout electronics; to achieve compactness and scalability, cryogenic integrated circuits have been recently proposed for this goal. Circulators are widely used in readout circuits, ho ...

2019

Fabrication and Characterisation of Epitaxial PMN-PT Nano-structures

Xiao Di

Downscaling of the minimal feature size, or the gate length has been the key for the exponential im-provement of the performance of the logic CMOS integrated circuits over the last six decades. How-ever, since about 2003, some fundamental limits in the dev ...

EPFL2019

JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS

Andreas Peter Burg, Seyed Armin Tajalli, Yusuf Leblebici, Firat Çelik, Ayça Akkaya

JESD204B compliant low-voltage differential signaling (LVDS), and source-series-terminated (SST) transmitters in 28 nm FD-SOI CMOS technology are presented with 1.1 pJ/bit and 1.7 pJ/bit at 12.5 Gb/s, respectively. An external 6.25 GHz single-ended clock, ...

IEEE2019

Exploring Lightweight Efficiency of Forkaes

Subhadeep Banik, Muhammed Fatih Balli

Recently the ForkAES construction was proposed by Andreeva et al. for efficiently performing authenticated encryption of very short messages on next generation IoT devices. The ForkAES tweakable block cipher uses around one and a half AES encryption calls ...

Springer2019

Microwave inductive proximity sensors with sub-pm/Hz1/2 resolution

Giovanni Boero, Nergiz Sahin Solmaz, Alessandro Valentino Matheoud, Lénaïc Frehner

Inductive proximity sensors are low-cost and versatile detectors achieving resolutions in the nm and sub-nm range. Their typical working frequency ranges from tens of kHz to a few MHz. Operation at higher frequencies is considered as a possible route for t ...

2019

Remotely-Powered Front-End at 2.45 GHz for Real-Time Continuous Temperature Sensing

Catherine Dehollain, Onur Kazanç, Franco Maloberti

Remote powering and power management of a passive sensor system employing antenna-rectifier co-design is presented. The operating frequency of the system is chosen at 2.45 GHz in order to reduce the antenna size. A co-design approach enables the coupling o ...

IEEE2018

Ramsey-mode Rb cell clock demonstration with a 3D-printed microwave cavity

Anja Skrivervik

We demonstrate operation of a Ramey-mode Rb vapor-cell atomic clock based on a microwave cavity realized by additive manufacturing (3D-printing). The cavity design is based on a loop-gap approach and its critical electrode structure is realized in one mono ...

2018

Automated Synthesis of Adversarial Workloads for Network Functions

Rishabh Ramesh Iyer, Aikaterini Argyraki, Arseniy Zaostrovnykh, Jonas Fietz, Luis David Figueiredo Mascarenhas Moreira Pedrosa

Software network functions promise to simplify the deployment of network services and reduce network operation cost. However, they face the challenge of unpredictable performance. Given this performance variability, it is imperative that during deployment, ...

ACM2018

A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End

Seyed Armin Tajalli, Yusuf Leblebici, Firat Çelik, Ayça Akkaya

This paper presents a low power successive approximation register (SAR) ADC and its front-end automatic gain control (AGC) amplifier designed in 65nm CMOS technology. Digitally controlled variable gain amplifier (VGA) in AGC loop is used to maximize the dy ...

IEEE2018

Page 2 of 2