Publications related to Pin grid array

Eco-Conscious Approach to Wireless Gas Monitoring With a Hybrid Printed Passive Sensor Tag

Sandro Carrara, Johanna Zikulnig, Jürgen Kosel

Addressing the environmental impact of electronic waste in biomedical sensing, an eco-conscious approach to the realization of a Chitosan-based Acetone sensor tag for wireless gas monitoring is presented. The fabrication involves inkjet printing of silver ...

Ieee-Inst Electrical Electronics Engineers Inc2024

Integrated silicon photonic MEMS

Niels Quack, Hamed Sattari, Alain Yuji Takabayashi

Silicon photonics has emerged as a mature technology that is expected to play a key role in critical emerging applications, including very high data rate optical communications, distance sensing for autonomous vehicles, photonic-accelerated computing, and ...

SPRINGERNATURE2023

Subharmonic parametric instability in nearly brimful circular cylinders: a weakly nonlinear analysis

François Gallaire, Alessandro Bongarzone, Francesco Viola

In labscale Faraday experiments, meniscus waves respond harmonically to small-amplitude forcing without threshold, hence potentially cloaking the instability onset of parametric waves. Their suppression can be achieved by imposing a contact line pinned at ...

Cambridge University Press2022

Generation of Human iPSC-Derived Neurons on Nanowire Arrays Featuring Varying Lengths, Pitches, and Diameters

Anna Fontcuberta i Morral, Wonjong Kim

Nanowire (NW) arrays interfaced with biological cells have been demonstrated to be potent tools for advanced applications such as sensing, stimulation, or drug delivery. Many implementations, however, have so far only been studied with rather robust basic ...

WILEY2022

Characterization and Modeling of Mismatch in Cryo-CMOS

Edoardo Charbon, Fabio Sebastiano

This paper presents a device matching study of a commercial 40-nm bulk CMOS technology operated at cryogenic temperatures. Transistor pairs and linear arrays, optimized for device matching, were characterized over the temperature range from 300 K down to 4 ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

System, device and method for quantum correlation measurement with single photon avalanche diode arrays

Edoardo Charbon, Claudio Bruschini, Ivan Michel Antolovic

A system for photon correlation of an illuminated object and/or a light source, including a light source for illuminating the object or to correlate, an optical system having an object-facing side configured to face the object or the light source and a pro ...

2020

Spatial coherence properties of an LED-based illumination system for mask-aligner lithography

Hans Peter Herzig, Toralf Scharf, Wilfried Noell, Raoul Kirner, Johana Bernasconi

A high-power LED-based illumination system has been developed as a replacement for the mercury arc lamps used in mask-aligner lithography. LEDs are arranged in a grid array and placed in the entrance aperture of individual reflectors. Those reflectors decr ...

SPIE2019

Modeling and Analysis of a Direct Time-of-Flight Sensor Architecture for LiDAR Applications

Edoardo Charbon, Chunmin Zhang, Preethi Padmanabhan

Direct time-of-flight (DTOF) is a prominent depth sensing method in light detection and ranging (LiDAR) applications. Single-photon avalanche diode (SPAD) arrays integrated in DTOF sensors have demonstrated excellent ranging and 3D imaging capabilities, ma ...

2019

Monolithic SPAD Arrays for High-Performance, Time-Resolved Single-Photon Imaging

Edoardo Charbon, Claudio Bruschini, Samuel Burri, Ivan Michel Antolovic, Arin Can Ülkü, Scott Anthony Lindner, Chunmin Zhang, Martin Wolf

SPAD (single-photon avalanche diode) arrays are single-photon sensors, which enable photon counting and unparalleled time-resolved imaging. In this paper, we will detail the architecture and characteristics of three representative SPAD arrays, implemented ...

IEEE2018

Organoid arrays

Matthias Lütolf, Nathalie Brandenberg

The invention provides methods for producing arrays of organoids, the arrays thereof and uses of such arrays. ...

2018

A Compact Modular Soft Surface With Reconfigurable Shape and Stiffness

Jamie Paik, Matthew Aaron Robertson, Wyatt Marshall Felt, Masato Murakami

A variety of reconfigurable surface devices, utilizing large numbers of actuated physical pixels to produce discretized 3D contours, have been developed for different purposes in research and industry. The difficulty of integrating many actuators in close ...

2018

A Chip-Level Post-CMOS Via-Last Cu TSV Process for Multi-Layer Homogeneous 3D Integration

Seniz Esra Küçük, Yusuf Leblebici, Woo Yeong Cho

In this paper, a die-level CMOS post-processing scheme for 3D integration using the via-last approach is presented for multi-layer stacking. The process includes TSV fabrication, chip-to-chip bonding, and finally the TSV filling with Cu electroplating. The ...

Ieee2016

Analyzing blinking effects in super resolution localization microscopy with single-photon SPAD imagers

Edoardo Charbon, Claudio Bruschini, Samuel Burri, Ivan Michel Antolovic

For many scientific applications, electron multiplying charge coupled devices (EMCCDs) have been the sensor of choice because of their high quantum efficiency and built-in electron amplification. Lately, many researchers introduced scientific complementary ...

Spie-Int Soc Optical Engineering2016

High-resolution, large-area fabrication of compliant electrodes via laser ablation for robust, stretchable dielectric elastomer actuators and sensors

Herbert Shea, Samuel Rosset, Oluwaseun Adelowo Araromi

A key element in stretchable actuators, sensors and systems based on elastomer materials are compliant electrodes. While there exist many methodologies for fabricating electrodes on dielectric elastomers, very few succeed in achieve high-resolution pattern ...

Amer Chemical Soc2015

A 1 x 400 Backside-Illuminated SPAD Sensor With 49.7 ps Resolution, 30 pJ/Sample TDCs Fabricated in 3D CMOS Technology for Near-Infrared Optical Tomography

Edoardo Charbon, Scott Anthony Lindner, Juan Mata Pavia, Martin Wolf

A 1 x 400 array of backside-illuminated SPADs fabricated in 130 nm 3D IC CMOS technology is presented. Sensing is performed in the top tier substrate and time-to-digital conversion in the bottom tier. Clusters of eight pixels are connected to a winner-take ...

Ieee-Inst Electrical Electronics Engineers Inc2015

Growth mechanisms of III-V semiconductor nanostructures on silicon

Eleonora Russo

The aim of this thesis is to understand the dynamics of the growth of catalyst-free III-V semiconductor nanostructures on silicon substrates, focusing the attention mainly on the early stages of growths. A detailed understanding of this first phase of the ...

EPFL2015

Nanowire systems: technology and design (invited paper)

Giovanni De Micheli, Davide Sacchetto, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon, Shashi Kanth Bobba, Michele De Marchi

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this work, we consider double independent gate, vertically-stacked nanowire FETs with gate-all-around structures and typical diameter of 20-nm. These devices, which we hav ...

Royal Soc2014

Wafer-fused VECSELs emitting in the 1310 nm waveband

Elyahou Kapon, Nicolas Volet, Alexandru Mereuta, Vladimir Iakovlev, Alexei Sirbu, Andrei Caliman, Kamil Pawel Pierscinski

Optically pumped wafer fused 1310 nm VECSELs have the advantage of high output power and wavelength agility. Gain mirrors in these lasers are formed by direct bonding of InAlGaAs/InP active cavities to Al(Ga) As/GaAs DBRs. We present for the first time Wat ...

Spie-Int Soc Optical Engineering2014

Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography

Carlotta Guiducci, Yusuf Leblebici, Yüksel Temiz

This paper presents a chip-level postcomplementary metal oxide semiconductor (CMOS) processing technique for 3-D integration and through-silicon-via (TSV) fabrication. The proposed technique is based on dry-film lithography, which is a low-cost and simple ...

Ieee-Inst Electrical Electronics Engineers Inc2013

A CMOS Compatible Chip-to-Chip 3D Integration Platform

Carlotta Guiducci, Michail Zervas, Yusuf Leblebici, Yüksel Temiz

In this paper, a CMOS-compatible chip-to-chip 3D integration platform will be presented. The developed technology allows reconstituting a wafer from diced and thinned chips. Then, chip-to-chip bonding and TSV fabrication steps are accomplished in wafer-lev ...

IEEE2012