Publications related to Rate-monotonic scheduling

OASIS: An integrated optimisation framework for activity scheduling

Activity-based models offer the potential for a far deeper understanding of daily mobility behaviour than trip-based models. Based on the fundamental assumption that travel demand is derived from the need to do activities, they are flexible tools that aim ...

EPFL2024

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

Simulating intra-household interactions for in- and out-of-home activity scheduling

Michel Bierlaire, Timothy Michael Hillel, Negar Rezvany

Various interactions, time arrangements, and constraints exist for individuals scheduling their day as a member of a household, which affect their in-home as well as out-of-home activity schedule. However, the existing activity-based models are mostly base ...

Pergamon-Elsevier Science Ltd2023

Learning to Align Sequential Actions in the Wild

Pascal Fua, Bugra Tekin, Weizhe Liu

State-of-the-art methods for self-supervised sequential action alignment rely on deep networks that find correspon- dences across videos in time. They either learn frame-to- frame mapping across sequences, which does not leverage temporal information, or a ...

IEEE COMPUTER SOC2022

From C/C plus plus Code to High-Performance Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis

Paolo Ienne, Lana Josipovic

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Equinox: Training (for Free) on a Custom Inference Accelerator

Babak Falsafi, Martin Jaggi, Ahmet Caner Yüzügüler, Louis Coulon, Mario Paulo Drumond Lages De Oliveira, Arash Pourhabibi Zarandi

DNN inference accelerators executing online services exhibit low average loads because of service demand variability, leading to poor resource utilization. Unfortunately, reclaiming idle inference cycles is difficult as other workloads can not execute on a ...

ACM2021

High-Level Synthesis of Dynamically Scheduled Circuits

Lana Josipovic

High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. These tools almost universally build datapaths that are controlled using a centralized controller which relies on a static, compile-time schedule to determine ...

EPFL2021

Combining Dynamic & Static Scheduling in High-level Synthesis

Paolo Ienne, Lana Josipovic

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

ASSOC COMPUTING MACHINERY2020

Thread-Placement Learning

Rachid Guerraoui, Vasileios Trigonakis, Karolos Antoniadis

In a non-uniform memory access machine, the placement of software threads to hardware cores can have a significant effect on the performance of concurrent applications. Detecting the best possible placement for each application is a necessity for thread sc ...

IEEE COMPUTER SOC2020

Adaptive HTAP through Elastic Resource Scheduling

Anastasia Ailamaki, Syed Mohammad Aunn Raza, Periklis Chrysogelos, Angelos Christos Anadiotis

Modern Hybrid Transactional/Analytical Processing (HTAP) systems use an integrated data processing engine that performs analytics on fresh data, which are ingested from a transactional engine. HTAP systems typically consider data freshness at design time, ...

2020

Adaptive HTAP through Elastic Resource Scheduling

Anastasia Ailamaki, Syed Mohammad Aunn Raza, Periklis Chrysogelos, Angelos Christos Anadiotis

Modern Hybrid Transactional/Analytical Processing (HTAP) systems use an integrated data processing engine that performs analytics on fresh data, which are ingested from a transactional engine. HTAP systems typically consider data freshness at design time, ...

ASSOC COMPUTING MACHINERY2020

Task scheduling for highly concurrent analytical and transaction workloads

Anastasia Ailamaki, Iraklis Psaroudakis

Systems and method for a task scheduler with dynamic adjustment of concurrency levels and task granularity are disclosed for improved execution of highly concurrent analytical and transactional systems. The task scheduler can avoid both over commitment and ...

2020

Can Dynamic Priority Be Pareto Improving?

Nikolaos Geroliminis, Raphael Ali Francis Lamotte

Traditional priority schemes reduce delays for some by increasing those of others. Yet, this might not be a necessity. Several works published over the last two decades have shown for a stylized set-up with homogeneous users that dynamic priority scheme ma ...

2020

ColTraIn: Co-located DNN training and inference

Mario Paulo Drumond Lages De Oliveira

Deep neural network inference accelerators are deployed at scale to accommodate online services, but face low average load because of service demand variability, leading to poor resource utilization. Unfortunately, reclaiming inference idle cycles is diffi ...

EPFL2020

Efficient Protocols for Enforcing Causal Consistency in Geo-Replicated Key-Value Data Stores

Kristina Spirovska

Modern large-scale data platforms manage colossal amount of data, generated by the ever-increasing number of concurrent users. Geo-replicated and sharded key-value data stores play a central role when building such platforms. As the strongest consistency m ...

EPFL2020

Speculative Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

With FPGAs facing broader application domains, the conversion of imperative languages into dataflow circuits has been recently revamped as a way to overcome the conservatism of statically scheduled high-level synthesis. Apart from the ability to extract pa ...

ASSOC COMPUTING MACHINERY2019

Bridging the gap between dataplanes and commodity operating systems

Georgios Prekas

The conventional wisdom is that aggressive networking requirements, such as high packet rates for small messages and microsecond-scale tail latency, are best addressed outside the kernel, in a user-level networking stack. In particular, dataplanes borrow d ...

EPFL2018

Hybrid, Job-Aware, and Preemptive Datacenter Scheduling

Pamela Isabel Delgado Borda

Scheduling in datacenters is an important, yet challenging problem. Datacenters are composed of a large number, typically tens of thousands, of commodity computers running a variety of data-parallel jobs. The role of the scheduler is to assign cluster reso ...

EPFL2018

A Framework Based on Predictive Maintenance, Zero-Defect Manufacturing and Scheduling Under Uncertainty Tools, to Optimize Production Capacities of High-End Quality Products

Dimitrios Kyritsis

Nowadays exploiting the full potential of the humongous amount of data that manufactures can produce with their production means is a real challenge. Moreover, increasing production capabilities without large investments is a recurring objective for them. ...

SPRINGER-VERLAG BERLIN2018