Publications related to Signal integrity

A Delay and Power Efficient Voltage Level Shifter with Low Leakage Power

This paper presents a new power-efficient and high-speed voltage level shifter. In the proposed structure, the existing contentions at the internal nodes are reduced using auxiliary transistors and feedback networks, leading to a significant reduction in t ...

IEEE2023

Electronic metadevices for terahertz applications

Elison de Nazareth Matioli, Mohammad Samizadeh Nikooytabalvandani

The evolution of electronics has largely relied on downscaling to meet the continuous needs for faster and highly integrated devices(1). As the channel length is reduced, however, classic electronic devices face fundamental issues that hinder exploiting ma ...

NATURE PORTFOLIO2023

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Stefan Nikolic

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

EPFL2023

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Edoardo Charbon, Claudio Bruschini, Andrei Ardelean, Paul Mos, Arin Can Ülkü, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gate ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Energy-Efficient Design Techniques for High-Speed Wireline Serial Links

Firat Çelik

The exponential growth in computing power and multimedia services has caused a tremendous increase in data traffic in recent years. This increase in data traffic brings a strong demand for data bandwidth of electrical input/output (I/O) links and pushes th ...

EPFL2021

Closing Leaks: Routing Against Crosstalk Side-Channel Attacks

Mirjana Stojilovic, Seyedeh Sharareh Mirzargar, Zeinab Seifoori

This paper presents an extension to PathFinder FPGA routing algorithm, which enables it to deliver FPGA designs free from risks of crosstalk attacks. Crosstalk side-channel attacks are a real threat in large designs assembled from various IPs, where some I ...

2020

Simulation of CMOS APS Operation and Crosstalk in SPICE With Generalized Devices

Jean-Michel Sallese, Chiara Rossi

We present SPICE simulations of a CMOS APS pixel element consisting of the optical sensor with the sensing circuit. The photodiode is simulated at the physics level by means of the so-called Generalized Devices, without any predefined compact model. Conver ...

2020

JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS

Andreas Peter Burg, Seyed Armin Tajalli, Yusuf Leblebici, Firat Çelik, Ayça Akkaya

JESD204B compliant low-voltage differential signaling (LVDS), and source-series-terminated (SST) transmitters in 28 nm FD-SOI CMOS technology are presented with 1.1 pJ/bit and 1.7 pJ/bit at 12.5 Gb/s, respectively. An external 6.25 GHz single-ended clock, ...

IEEE2019

Triggered incommensurate transition in PbHfO3

Alexander Tagantsev

We report a type of structural phase transitions in dielectric materials: the triggered incommensurate (IC) transition. We demonstrate evidence for such a transition in the perovskite antiferroelectric PbHfO3 by means of single-crystal x-ray diffraction, d ...

AMER PHYSICAL SOC2019

A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman, Jeremy Hugues-Felix Constantin

The increasing impact of variability on near-threshold nanometer circuits calls for a tighter online monitoring and control of the available timing margins. Error-detection sequentials are widely used together with error-correction techniques to operate di ...

IEEE2018

Circuit Design, Architecture and CAD for RRAM-based FPGAs

Xifan Tang

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two ...

EPFL2017

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay, Zheng Wang

This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. In contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circ ...

ACM2016

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay, Zheng Wang

This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. hi contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circ ...

Ieee2016

Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

A 3-D simulation of substrate currents is crucial to analyze parasitic coupling effects due to minority carrier injection in smart power ICs. In this paper, a substrate parasitic extraction methodology is introduced by dividing the IC layout into elementar ...

Ieee-Inst Electrical Electronics Engineers Inc2016

The EPFL Combinational Benchmark Suite

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

In this paper, we present the EPFL combinational benchmark suite. We aim at completing existing benchmark suites by focusing only on natively combinational benchmarks. The EPFL combinational benchmark suite consists of 23 combinational circuits desi ...

2015

Spice Simulation of Passive Protection in Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

When designing in Smart Power technologies, TCAD simulations are mandatory to design effective passive protections against parasitic couplings due to minority carriers. The objective of this paper is to propose a spice-based approach to characterize electr ...

Ieee2015

Infrared Vibrational Molecular Hybridization with a Single Optical Antenna

Hatice Altug

We observe impedance matched coupling between molecular vibrations and infrared optical antennas. Broadband synchrotron near-field spectroscopy reveals antenna-vibration hybridization, mode splitting, and tip excitation of coupled dark plasmon modes. ...

IEEE2015

A Subthreshold Current-Sensing Sigma-Delta Modulator for Low-Voltage and Low-Power Sensor Interfaces

Alexandre Schmid, Seyed Armin Tajalli, Yusuf Leblebici, Nikola Katic

A continuous-time (CT) ΣΔ modulator for sensing and direct analog-to-digital conversion of nA-range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source-coupled logic cells to ...

Wiley2015

Submicrometer Organic Thin-Film Transistors: Technology Assessment Through Noise Margin Analysis of Inverters

Christian Enz, Jean-Michel Sallese, Rolando Ferrini, Franz Xaver Pengg, Nenad Marjanovic, Frédéric Zanella

In this paper, we propose a methodology to evaluate the potential of submicrometer organic thin-film transistors (OTFTs) with nanoimprinted gate and self-aligned source and drain contacts. In the first step, the dedicated static model we previously reporte ...

Institute of Electrical and Electronics Engineers2014

Parallel vs. Serial Inter-plane communication using TSVs

Giovanni De Micheli, Yusuf Leblebici, Somayyeh Rahimian Omam

3-D integration is a promising prospect for implementing high performance multifunctional systems-on- chip. Through Silicon Vias (TSVs) are the enablers for achieving high bandwidth paths in inter-plane communications. TSVs also provide higher vertical lin ...

2014