Publications related to Transistor model

Exploring negative capacitance and neuromorphic devices based on CMOS-compatible ferroelectric HfO2

Ferroelectric materials are explored for numerous applications thanks to their properties associated with electrically switchable spontaneous polarization. Perovskites are an established class of ferroelectrics used for sensors and actuators. However, they ...

EPFL2022

Cryogenic MOSFET Modeling for Large-Scale Quantum Computing

Arnout Lodewijk M Beckers

Promising results of state-of-the-art quantum computers fuel a world-wide effort in academic and private research laboratories to scale up the number of qubits and improve their characteristics in large arrays. To meet the scale-up challenge, innovative mi ...

EPFL2021

Low Noise Clock Generation: Modeling, Analysis and Implementation

Duygu Kostak

The aim of this thesis is to implement, analyze and improve the selected low noise clock generation and distribution techniques for ADC implementations. The thesis is divided into two parts. The first part focuses on the sampling phase generation and distr ...

EPFL2021

Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing

Paolo Ienne, Grace Zgheib, Stefan Nikolic

Technology scaling makes metal delay ever more problematic, but routing between Look-Up Tables (LUTs) still passes through a series of transistors. It seems wise to avoid the corresponding delay whenever possible. Direct connections between LUTs, both with ...

ASSOC COMPUTING MACHINERY2020

Comparison of Different Precision Pseudo Resistor Realizations in the DC-Feedback of Capacitive Transimpedance Amplifiers

Georg Fantner, Jens Anders

In this paper, three different pseudo resistor (PR) realizations are compared regarding their noise and linearity performance within the DC feedback loop of an integrator-differentiator transimpedance amplifier (I-D-TIA). Thanks to its intrinsic shot noise ...

IEEE2019

Conformal Deposition of Conductive Single-Crystalline Cobalt Silicide Layer on Si Wafer via a Molecular Approach

Giovanni De Micheli, Olha Sereda, Pierre-Emmanuel Julien Marc Gaillardon, Tsung-Han Lin, David Baudouin

The realization of metal-semiconductor contacts plays a significant role in ultrascaled integrated circuits. Here, we establish a low-temperature molecular approach for the conformal deposition of a 20-nm Co-rich layer on Si (100) wafers by reaction in sol ...

2018

Low Temperature Wet Conformal Nickel Silicide Deposition for Transistor Technology through an Organometallic Approach

Giovanni De Micheli, Michele De Marchi, Pierre-Emmanuel Julien Marc Gaillardon, Maxime Victor Thammasack, Tsung-Han Lin, David Baudouin

The race for performance of integrated circuits is nowadays facing a downscale limitation. To overpass this nanoscale limit, modern transistors with complex geometries have flourished, allowing higher performance and energy efficiency. Accompanying this br ...

Amer Chemical Soc2017

Variability of Low Frequency Noise and mismatch in enclosed-gate and standard nMOSFETs

Matthias Bucher, Mathieu Yves Hervé Coustans

Variability of Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) is an important concern for many analog CMOS integrated circuits. In this paper, transistors with enclosed gate layout are examined and compared with standard layout transistors, wit ...

IEEE2017

Conformal Mapping of Impedance Stability Models for System-Level Dynamics Assessments

Drazen Dujic, Francisco Daniel Freijedo Fernández, Uzair Javaid

Impedance stability methods are suitable for assessing the dynamics of power converters controllers, but also for ac/dc microgrids system level studies. This work proposes the combination of impedance modeling and conformal mapping for the identification o ...

2017

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Oskar Andersson

In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch a ...

Institute of Electrical and Electronics Engineers2016

Modeling Parasitic Vertical PNP in HVCMOS

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

High voltage CMOS active devices inherently have a parasitic vertical bipolar transistor. The parasitic PNP structure can be activated during high-power switching operation causing a potential shift of the substrate. In this work a spice-modeling approach ...

IEEE2015

Kerr coefficients of plasma resonances in Josephson junction chains

We present an experimental and theoretical analysis of the self-and cross-Kerr effect of extended plasma resonances in Josephson junction chains. We calculate the Kerr coefficients by deriving and diagonalizing the Hamiltonian of a linear circuit model for ...

Amer Physical Soc2015

New Data Structures and Algorithms for Logic Synthesis and Verification

Luca Gaetano Amarù

The strong interaction between Electronic Design Automation (EDA) tools and Complementary Metal-Oxide Semiconductor (CMOS) technology contributed substantially to the advancement of modern digital electronics. The continuous downscaling of CMOS Field Effec ...

EPFL2015

Nanowire systems: technology and design (invited paper)

Giovanni De Micheli, Davide Sacchetto, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon, Shashi Kanth Bobba, Michele De Marchi

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this work, we consider double independent gate, vertically-stacked nanowire FETs with gate-all-around structures and typical diameter of 20-nm. These devices, which we hav ...

Royal Soc2014

Phase-locked loop based on nanoelectromechanical resonant-body field effect transistor

Mihai Adrian Ionescu, Alexandru Rusu, Sebastian Thimotee Bartsch

We demonstrate the room-temperature operation of a silicon nanoelectromechanical resonant-body field effect transistor (RB-FET) embedded into phase-locked loop (PLL). The very-high frequency resonator uses on-chip electrostatic actuation and transistor-bas ...

American Institute of Physics2012

Substrate Current Modeling for high Temperature Smart Power BCD Technology

Fabrizio Lo Conte

The electronics industry is present nowadays in the most various applications. A new type of technology for integrated circuits named BCD has started to be developed and appeared from the mid 1980’s. This new technology allows integrating bipolar transisto ...

EPFL2012

A programmable triangular neighborhood function for a Kohonen self-organizing map implemented on chip

Rafal Tomasz Dlugosz

An efficient transistor level implementation of a flexible, programmable Triangular Function (TF) that can be used as a Triangular Neighborhood Function (TNF) in ultra-low power, self-organizing maps (SOMs) realized as Application-Specific Integrated Circu ...

2012

Standard-Cell Based Memories (SCMs): from Sub-VT to Error-Resilient Systems

Andreas Peter Burg, Pascal Andreas Meinerzhagen

Embedded memories consume an increasingly dominant part of the overall area and power of a large variety of systems-on-chip [ITRS’09]: 1) biomedical implants and wireless sensor networks require robust memories operating in the sub-VT domain; 2) many handh ...

2012

Process Variation and Leakage Power

Bahman Kheradmand Boroujeni

Technology scaling improves the energy, performance, and area of the digital circuits. With further scaling into sub-45nm regime, we are moving toward very low supply (VDD) and threshold voltages (VT), smaller VDD/VT ratio, high leakage current, and large ...

EPFL2011

In-IC Strategies for 3D Devices in Bulk Silicon

Matthieu Bopp

The increase of components density in advanced microelectronics is practically dictated by the device size and the achievable pitch between the devices. Scaling down dimensions of devices and progress in the circuit design allowed following Moore's law dur ...

EPFL2011