Diode–transistor logic

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Related publications (29)

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Oskar Andersson

In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch a ...

Institute of Electrical and Electronics Engineers2016

Synthesis, Morphological, and Electro-optical Characterizations of Metal/Semiconductor Nanowire Heterostructures

Anna Fontcuberta i Morral, Sonia Conesa Boj, Heidi Andrea Potts

In this letter, we demonstrate the formation of unique Ga/GaAs/Si nanowire heterostructures, which were successfully implemented in nanoscale light-emitting devices with visible room temperature electroluminescence. Based on our recent approach for the int ...

American Chemical Society2016

Substrate modeling of parasitic couplings in Smart Power ICs with generalized lumped devices

Camillo Stefanucci

Today automotive industry is demanding more and more compact solutions for embedded electronics to be interfaced with vehicles components such as motor drivers, igniters and car communication buses. That is why Smart Power Integrated Circuits (IC) have bee ...

EPFL2016

Exploiting Circuit Duality to Speed Up SAT

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Maciej Jerzy Ciesielski

In this paper, we establish a non-trivial duality between tautology and contradiction check to speed up circuit SAT. Tautology check determines if a logic circuit is true in every possible interpretation. Analogously, contradiction check dete ...

IEEE2015

Polarity Control at Runtime : from Circuit Concept to Device Fabrication

Michele De Marchi

Semiconductor device research for digital circuit design is currently facing increasing challenges to enhance miniaturization and performance. A huge economic push and the interest in novel applications are stimulating the development of new pathways to ov ...

EPFL2015

Modeling Minority Carriers Related Capacitive Effects for Transient Substrate Currents in Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

This paper presents an extended model for transient and ac circuit-level simulation of minority carriers propagation through the substrate of smart power integrated circuits (ICs). A p-n junction and a diffusion resistor with capacitive components are prop ...

Institute of Electrical and Electronics Engineers2015

Modeling Parasitic Vertical PNP in HVCMOS

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

High voltage CMOS active devices inherently have a parasitic vertical bipolar transistor. The parasitic PNP structure can be activated during high-power switching operation causing a potential shift of the substrate. In this work a spice-modeling approach ...

IEEE2015

A charge carrier transport model for donor-acceptor blend layers

Wolfgang Richard Tress

Highly efficient organic solar cells typically comprise donor-acceptor blend layers facilitating effective splitting of excitons. However, the charge carrier mobility in the blends can be substantially smaller than in neat materials, hampering the device p ...

American Institute of Physics2015

Shallow donor and deep DX-like center in InAlN layers nearly lattice-matched to GaN

Nicolas Grandjean, Jean-François Carlin, Marcel Py, Lorenzo Lugani

Nonintentionally doped 200-nm-thick In0.16Al0.84N/n(+)-GaN samples were grown by metal-organic vapor phase epitaxy and used for the electrical characterization of InAlN. In the temperature range 180-400 K, the forward current of Schottky diodes is dominate ...

Amer Physical Soc2014

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