Publications related to Adder (electronics)

RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks

Mirjana Stojilovic, Ognjen Glamocanin, David Spielmann

State-of-the-art sensors for measuring FPGA voltage fluctuations are time-to-digital converters (TDCs). They allow detecting voltage fluctuations in the order of a few nanoseconds. The key building component of a TDC is a delay line, typically implemented ...

2023

Technology Mapping Using Multi-output Library Cells

Giovanni De Micheli, Alessandro Tempia Calvino

Technology mapping transforms a technology-independent representation into a technology-dependent one given a library of cells. Even if technology libraries contain multi-output cells, state-of-the-art techniques fully exploit single-output cells only. Mul ...

2023

Periodic and Aperiodic NiFe Nanomagnet/Ferrimagnet Hybrid Structures for 2D Magnon Steering and Interferometry with High Extinction Ratio

Dirk Grundler, Sho Watanabe, Andrea Mucchietto, Shixuan Shan, Elif Nur Dayi, Vinayak Shantaram Bhat

Magnons, quanta of spin waves, are known to enable information processing with low power consumption at the nanoscale. So far, however, experimentally realized half-adders, wave-logic and binary output operations were based on few µm-long spin waves and re ...

Wiley2023

Effects of Degrees of Freedom on Calculating Diffusion Properties in Nanoporous Materials br

Berend Smit, Raffaela Cabriolu, Henglu Xu

If one carries out a molecular simulation ofNparticlesusing periodic boundary conditions, linear momentum is conserved,and hence, the number of degrees of freedom is set to 3N-3. Inmost programs, this number of degrees of freedom is the defaultsetting. How ...

AMER CHEMICAL SOC2022

Further Results on Efficient Implementations of Block Cipher Linear Layers

Subhadeep Banik

At the FSE conference of ToSC 2018, Kranz et al. presented their results on shortest linear programs for the linear layers of several well known block ciphers in literature. Shortest linear programs are essentially the minimum number of 2-input xor gates r ...

2021

Reconfigurable Logic Gates Based on Programable Multistable Mechanisms

Simon Nessim Henein, Hubert Pierre-Marie Benoît Schneegans, Ilan Vardi, Mohamed Gamal Abdelrahman Ahmed Zanaty

Binary logic gates are building blocks of computing machines, in particular, electronic computers. One variant is the programable logic gate, also known as the reconfigurable logic gate, in which the logical function implemented can be modified. In this pa ...

2020

More Results on Shortest Linear Programs

Subhadeep Banik

At the FSE conference of ToSC 2018, Kranz et al. presented their results on shortest linear programs for the linear layers of several well known block ciphers in literature. Shortest linear programs are essentially the minimum number of 2-input xor gates r ...

2019

Polarity-Controllable Devices and Circuits for Doping-Free 2D Electronics

Giovanni Vincenzo Resta

The growth of information technology has been sustained by the miniaturization of Complementary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors (FETs), with the number of devices per unit area constantly increasing, as exemplified by Mooreâ s la ...

EPFL2019

Adaptive simulation-based framework for error characterization of inexact circuits

Vincent Frédéric Camus

To design faster and more energy-efficient systems, numerous inexact arithmetic operators have been proposed, generally obtained by modifying the logic structure of conventional circuits. However, as the quality of service of an application has to be ensur ...

PERGAMON-ELSEVIER SCIENCE LTD2019

CASSIS: Characterization with Adaptive Sample-Size Inferential Statistics Applied to Inexact Circuits

Vincent Frédéric Camus

To design faster and more energy-efficient systems, numerous inexact arithmetic operators have been proposed, generally obtained by modifying the logic structure of conventional circuits. However, as the quality of service of an application has to be ensur ...

2018

Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

Christian Enz, Vincent Frédéric Camus, Jérémy Lucien Maurice Schlachter, Mattia Cacciotti

This paper introduces a novel method for designing approximate circuits by fabricating and exploiting false timing paths, i.e. critical paths that cannot be logically activated. This allows to strongly relax timing constraints while guaranteeing minimal an ...

2018

Doping-Free Complementary Logic Gates Enabled by Two-Dimensional Polarity-Controllable Transistors

Giovanni De Micheli, Giovanni Vincenzo Resta, Pierre-Emmanuel Julien Marc Gaillardon

Atomically thin two-dimensional (2D) materials belonging to transition metal dichalcogenides, due to their physical and electrical properties, are an exceptional vector for the exploration of next-generation semiconductor devices. Among them, due to the po ...

2018

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains

Giovanni De Micheli, Paolo Ienne, Mathias Soeken, Grace Zgheib, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon, Ana Petkovska, Luca Gaetano Amarù, Zhufei Chu

Hard-wired carry chains in FPGAs are designed to improve efficiency of important arithmetic primitives. Although they are proven to be effective for arithmetic-rich functions, there are very few studies on the optimization opportunities of carry chains for ...

ACM2017

Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies

Giovanni De Micheli, Mathias Soeken, Eleonora Testa, Odysseas Zografos

Traditional logic synthesis faces challenges of meeting the requirements demanded by the many emerging nanotech-nologies that are based on logic models different from standard CMOS. Several emerging nanodevices including Quantum-dot Cellular Automata (QCA) ...

IEEE2017

Thermal Issues in Deep Sub-Micron FDSOI Circuits

Yusuf Leblebici, Can Baltaci

Self-heating effects became more prominent with the introduction of the modern devices like FDSOI and low thermal conductivity materials such as SiO2. Consequently, the design of high speed digital circuits which are the time-critical blocks of high perfor ...

Ieee2016

A Fast Pruning Technique for Low-Power Inexact Circuit Design

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Jaime Joven Murillo, Johan Broc

Inexact Circuits are circuits in which the accuracy of the output can be traded for cost savings (energy, area and/or delay). In the context of advanced technology scaling and power density increase, inexact circuits appear to be very promising as ...

IEEE2015

Polarity Control at Runtime : from Circuit Concept to Device Fabrication

Michele De Marchi

Semiconductor device research for digital circuit design is currently facing increasing challenges to enhance miniaturization and performance. A huge economic push and the interest in novel applications are stimulating the development of new pathways to ov ...

EPFL2015

A New Basic Logic Structure for Data-Path Computation

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

Nowadays, Field Programmable Gate Arrays (FPGA) implement arithmetic functions using specific circuits at the logic block level, such as the carry paths, or at the structure level adopting Digital Signal Processing (DSP) blocks. Nevertheless, all these app ...

2014

Compressor Tree Synthesis on Commercial High-Performance FPGAs

Paolo Ienne, Philip Brisk, Hadi Parandeh Afshar

Compressor trees are a class of circuits that generalizes multioperand addition and the partial product reduction trees of parallel multipliers using carry-save arithmetic. Compressor trees naturally occur in many DSP applications, such as FIR filters, and ...

2011

Design Aspects of Carry Lookahead Adders with Vertically-Stacked Nanowire Transistors

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Mohamed Haykel Ben Jamaa

This paper discusses the newly introduced vertically-stacked silicon nanowire gate-all-around fieldeffect-transistor technology and its advantages for higher density layout design. The vertical nanowire stacking technology allows very-high density arrangem ...

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