Publications by Paolo Ienne | EPFL Graph Search

The Rise and Fall of Automatic Instruction-Set Extensions

Customizable processors—which allowed their instruction set architecture (ISA) to be augmented with applicationspecific custom instruction set extensions (ISEs)—arrived on the market at the turn of the millenium. Commercial offerings included the Tensilica ...

IEEE2025

ElasticMiter: Formally Verified Dataflow Circuit Rewrites

Paolo Ienne, Ayatallah Ahmed Gamal Kamal Elakhras

Dataflow circuits have been studied for decades as a way to implement both asynchronous and synchronous designs, and, more recently, have attracted attention as the target of high-level synthesis (HLS) compilers. Yet, little is known about mechanisms to sy ...

ACM2025

HBMex: An Attachment for Nonbursting Accelerators to Enhance HBM Performance

Paolo Ienne

Modern FPGAs integrate High Bandwidth Memory (HBM), offering up to 12× the DDR bandwidth distributed across multiple memory interfaces. To utilize the most of HBM's theoretical bandwidth, accelerators typically issue long bursts and exploit data locality. ...

Institute of Electrical and Electronics Engineers Inc.2025

DRSA: Accelerating Macro Placement on Commercial FPGAs

Paolo Ienne, Lana Josipovic, Andrea Guerrieri

PGAs are highly versatile devices, but their backend compilation process is significantly time-consuming. DynaRapid has demonstrated the potential to drastically reduce compilation times to mere seconds by leveraging macro-component-based design hierarchie ...

IEEE2025

FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis

Paolo Ienne, Mirjana Stojilovic, Louis Coulon

Reconfigurable computing fabrics include FPGAs and CGRAs. FPGAs offer flexible bit-level reconfigurability and can map almost any program via high-level synthesis (HLS) compilers, but they incur high area and speed overheads compared to ASICs. CGRAs, in co ...

ACM Association for Computing Machinery2025

FlexiMem: Flexible Shared Virtual Memory for PCIe-attached FPGAs

Paolo Ienne

Shared Virtual Memory (SVM) is a mechanism that allows host-side applications and FPGA accelerators to access the same virtual address space. It enables accelerating algorithms with unpredictable memory access patterns by making transparent pointer sharing ...

Institute of Electrical and Electronics Engineers Inc.2024

Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Ayatallah Ahmed Gamal Kamal Elakhras

Dynamically scheduled HLS, through dataflow circuit generation, has proven successful at exploiting operation-level parallelism in several important situations where statically scheduled HLS fails. Yet, although existing dataflow circuits support out-of-or ...

Association for Computing Machinery, Inc2024

HardCilk: Cilk-like Task Parallelism for FPGAs

Paolo Ienne

High-level synthesis (HLS) helps to develop hard-ware accelerators for field-programmable gate arrays (FPGAs) using C/C++ descriptions. HLS is tailored to exploit instruction-level parallelism and, where available, data-level parallelism in applications. Y ...

Institute of Electrical and Electronics Engineers Inc.2024

Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns

Paolo Ienne, Stefan Nikolic

Increased lower metal resistance makes physical aspects of Field-Programmable Gate Array (FPGA) switch-blocks more relevant than before. The need to navigate a design space where each individual switch can have significant impact on the FPGA's performance ...

2024

DynaRapid: Fast-Tracking from C to Routed Circuits

Paolo Ienne

Advancements in design automation technologies, such as high-level synthesis (HLS), have raised the input abstraction level and made the design entry process for FPGAs more friendly to software programmers. In contrast, the backend compilation process for ...

Institute of Electrical and Electronics Engineers Inc.2024

Regularity Matters: Designing Practical FPGA Switch-Blocks

Paolo Ienne, Stefan Nikolic

Several techniques have been proposed for automatically searching for FPGA switch-blocks which typically show some tangible advantage over the well-known academic architectures. However, the resulting switch-blocks usually exhibit high levels of irregulari ...

Assoc Computing Machinery2023

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles

Paolo Ienne, Kubilay Atasu, Jovan Blanusa

Finding cycles in directed graphs enables important applications in various domains such as finance, biology, chemistry, and network science. However, as the size of graph datasets continues to grow, it becomes increasingly difficult to discover cycles wit ...

arXiv2023

Resource Sharing in Dataflow Circuits

Paolo Ienne, Lana Josipovic, Andrea Guerrieri, Axel Marmet

To achieve resource-efficient hardware designs, high-level synthesis (HLS) tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed in conjunction with operation scheduling to ensure th ...

Assoc Computing Machinery2023

Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Ayatallah Ahmed Gamal Kamal Elakhras

Dynamically scheduled high-level synthesis can exploit high levels of parallelism in poorly-predictable control-dominated applications. Yet, dataflow circuits are often generated by literal conversion of basic blocks into circuits interconnected in such a ...

Assoc Computing Machinery2023

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles

Paolo Ienne, Kubilay Atasu, Jovan Blanusa

Cycles are one of the fundamental subgraph patterns and being able to enumerate them in graphs enables important applications in a wide variety of fields, including finance, biology, chemistry, and network science. However, to enable cycle enumeration in r ...

Assoc Computing Machinery2023

Introduction to the Special Section on FPGA 2022

Paolo Ienne

Assoc Computing Machinery2023

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

Paolo Ienne, Mikhail Asiatici

Applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on FPGAs due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by re ...

ASSOC COMPUTING MACHINERY2022

Detailed Placement for Dedicated LUT-Level FPGA Interconnect

Paolo Ienne, Grace Zgheib, Stefan Nikolic

In this work, we develop timing-driven CAD support for FPGA architectures with direct connections between LUTs. We do so by proposing an efficient ILP-based detailed placer, which moves a carefully selected subset of LUTs from their original positions, so ...

ASSOC COMPUTING MACHINERY2022

Scalable Fine-Grained Parallel Cycle Enumeration Algorithms

Paolo Ienne, Kubilay Atasu, Jovan Blanusa

2022

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits

Paolo Ienne, Lana Josipovic, Andrea Guerrieri, Carmine Rizzi

The ability of dataflow circuits to implement dynamic scheduling promises to overcome the conservatism of static scheduling techniques that high-level synthesis tools typically rely on. Yet, the same distributed control mechanism that allows dataflow circu ...

IEEE COMPUTER SOC2022