Publications by Paul Victor Georges Muller

A micro-solid oxide fuel cell system as battery replacement

Paul Victor Georges Muller, Paul Muralt, Samuel Rey-Mermet, Anna Infortuna, Dimos Poulikakos

2008

A Power-Efficient Clock and Data Recovery Circuit in 0.18-um CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

Paul Victor Georges Muller, Yusuf Leblebici, Seyed Armin Tajalli

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two ma ...

2007

Tradeoffs in Design of Low-Power Gated-Oscillator CDR Circuits

Paul Victor Georges Muller, Yusuf Leblebici, Seyed Armin Tajalli

This article describes some techniques for implementing low- power clock and data recovery (CDR) circuits based on gated- oscillator (GO) topology for short distance applications. Here, the main tradeoffs in design of a high performance and power-efficient ...

2007

Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs

Paul Victor Georges Muller, Yusuf Leblebici, Seyed Armin Tajalli

This paper presents an approach for analyzing and modeling of gated-oscillator (GO) -based CDRs and predicting their performance aspects such as jitter tolerance (JTOL) and frequency tolerance (FTOL). It is shown that high JTOL of this topology in addition ...

IEEE2006

Design and Integration of All-Silicon Fiber-Optic Receivers for Multi-Gigabit Chip-to-Chip Links

Paul Victor Georges Muller, Yusuf Leblebici, Seyed Armin Tajalli

This paper presents a top-down approach to the design of all-silicon CMOS-based fully integrated optical receivers. From the system-level requirements, we determine the optimum block-level specifications, based on which the individual building blocks are d ...

IEEE2006

A standard CMOS multi-channel single-chip receiver for multi-gigabit optical data communications

Paul Victor Georges Muller

As dictated by ongoing technology scaling and the advent of multi-core systems, each new generation of microprocessors and digital signal processors provides higher computing power and data throughput. However, the available bandwidth of the input/output ( ...

EPFL2006

A low-power, multichannel gated oscillator-based CDR for short-haul applications

Paul Victor Georges Muller, Yusuf Leblebici, Seyed Armin Tajalli

We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the topology down t ...

2005

Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit

Paul Victor Georges Muller, Yusuf Leblebici, Seyed Armin Tajalli

We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the topology down t ...

IEEE2005

A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18µm digital CMOS technology

Paul Victor Georges Muller, Yusuf Leblebici, Seyed Armin Tajalli

This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying ...

2005

Jitter Tolerance Analysis of Clock and Data Recovery Circuits using Matlab and VHDL-AMS

Paul Victor Georges Muller, Yusuf Leblebici

In the scope of the development of a complete top-down design flow targeting clock and data recovery circuits for high-speed data links, we present two methods to analyze the jitter tolerance of such links, based on statistical simulation of incoming data ...

2005

Limiting Amplifiers for Next-Generation Multi-Channel Optical I/O Interfaces in SoCs

Paul Victor Georges Muller, Yusuf Leblebici

We present two fully differential limiting amplifiers with and without inductive peaking, designed and integrated in 0.18mm digital CMOS technology. The key design trade-offs, the importance of inductive coupling between neighboring channels, as well as th ...

2005