Publications by Mirjana Stojilovic

Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox

Mirjana Stojilovic, Shashwat Shrivastava

Routing is one of the major challenges of FPGA compilation. PathFinder is a ubiquitous FPGA routing algorithm used in industry and academia due to its ability to adapt to arbitrary routing architectures and user circuits. However, to this day, we do not fu ...

2025

FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis

Paolo Ienne, Mirjana Stojilovic, Louis Coulon

Reconfigurable computing fabrics include FPGAs and CGRAs. FPGAs offer flexible bit-level reconfigurability and can map almost any program via high-level synthesis (HLS) compilers, but they incur high area and speed overheads compared to ASICs. CGRAs, in co ...

ACM Association for Computing Machinery2025

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

Mirjana Stojilovic, Wei Hu, Dina Gamaleldin Ahmed Shawky Mahmoud, Beatrice Shokry Samir Shokry

Cloud computing environments increasingly provision field-programmable gate arrays (FPGAs) for their programmability and hardware-level parallelism. While FPGAs are typically used by one tenant at a time, multitenant schemes supporting spatial sharing of c ...

2024

Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs

Mirjana Stojilovic, Ognjen Glamocanin, Mathias Josef Payer, Hajira Shafqat Bazaz

To answer the growing demand for hardware acceleration, Amazon, Microsoft, and many other major cloud service providers have included field-programmable gate arrays (FPGAs) in their datacenters. However, researchers have shown that cloud FPGAs, when shared ...

IEEE2023

RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks

Mirjana Stojilovic, Ognjen Glamocanin, David Spielmann

State-of-the-art sensors for measuring FPGA voltage fluctuations are time-to-digital converters (TDCs). They allow detecting voltage fluctuations in the order of a few nanoseconds. The key building component of a TDC is a delay line, typically implemented ...

2023

The Side-channel Metrics Cheat Sheet

Francesco Regazzoni, Mirjana Stojilovic, Dorian Ros, Ognjen Glamocanin

Side-channel attacks exploit a physical observable originating from a cryptographic device in order to extract its secrets. Many practically relevant advances in the field of side-channel analysis relate to security evaluations of cryptographic functions a ...

2023

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

Mirjana Stojilovic, Stefan Nikolic, Shashwat Shrivastava

We identified that in modern commercial FPGAs, routing signals from the general interconnect to the configurable logic blocks (CLBs) through a very sparse input interconnect block (IIB) represents a significant runtime bottleneck. This is despite academic ...

IEEE2023

A Visionary Look at the Security of Reconfigurable Cloud Computing

Francesco Regazzoni, Mirjana Stojilovic

Field-programmable gate arrays (FPGAs) have become critical components in many cloud computing platforms. These devices possess the fine-grained parallelism and specialization needed to accelerate applications ranging from machine learning to networking an ...

2023

Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

Francesco Regazzoni, Mirjana Stojilovic, Ognjen Glamocanin, Dina Gamaleldin Ahmed Shawky Mahmoud

Cloud computing environments increasingly provision FPGAs because of their fine-grained, highly parallel, and flexible hardware architecture. The availability of FPGAs in the cloud fueled research on the security risks associated with exposing FPGA fabric ...

Springer, Cham2023

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Mirjana Stojilovic, Ognjen Glamocanin, Mathias Josef Payer, Shashwat Shrivastava, Jinwei Yao, Nour Ardo

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

2023

Active Wire Fences for Multitenant FPGAs

Mirjana Stojilovic, Ognjen Glamocanin, Andela Kostic, Stasa Kostic

When spatially shared among multiple tenants, field-programmable gate arrays (FPGAs) are vulnerable to remote power side-channel analysis attacks. Using carefully crafted on-chip voltage sensors, adversaries can extract secrets (e.g., encryption keys or th ...

2023

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Mirjana Stojilovic, Ognjen Glamocanin, Mathias Josef Payer, Shashwat Shrivastava

This repository contains the design files and software required to reproduce the results in the paper "Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs" by Ognjen Glamocanin, Shashwat Shrivastava, Jinwei Yao, Nour A ...

EPFL Infoscience2023

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

Mirjana Stojilovic, Stefan Nikolic, Shashwat Shrivastava

This repository contains the data and software required to reproduce the results in the paper "IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck," by Shashwat Shrivastava (EPFL), Stefan Niko ...

Zenodo2023

GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors

Mirjana Stojilovic, Guanglei Zhou

A graph H is a minor of a second graph G if G can be transformed into H by two operations: 1) deleting nodes and/or edges, or 2) contracting edges. Coarse-grained reconfigurable array (CGRA) application mapping is closely related to the graph minor problem ...

Los Alamitos2023

A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time

Mirjana Stojilovic

Side-channel CPU disassembly is a side-channel attack that allows an adversary to recover instructions executed by a processor. Not only does such an attack compromise code confidentiality, it can also reveal critical information on the system’s internals. ...

IEEE2022

FPGA-to-CPU Undervolting Attacks

Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud

FPGAs are proving useful and attractive for many applications, thanks to their hardware reconfigurability, low power, and high-degree of parallelism. As a result, modern embedded systems are often based on systems-on-chip (SoCs), where CPUs and FPGAs share ...

IEEE2022

Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era

Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud

Given the need for efficient high-performance computing, computer architectures combining CPUs, GPUs, and FPGAs are nowadays prevalent. However, each of these components suffers from electrical-level security risks. Moving to heterogeneous systems, with th ...

2022

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

Mirjana Stojilovic, David Dervishi, Dina Gamaleldin Ahmed Shawky Mahmoud

Field-programmable gate arrays (FPGAs) combine hardware reconfigurability with a high degree of parallelism. Consequently, FPGAs offer performance gains and power savings for many applications. A recent trend has been to leverage the hardware versatility o ...

2022

Deep Learning Detection of GPS Spoofing

Mirjana Stojilovic, Olivia Jullian Parra

Unmanned aerial vehicles (UAVs) are widely deployed in air navigation, where numerous applications use them for safety-of-life and positioning, navigation, and timing tasks. Consequently, GPS spoofing attacks are more and more frequent. The aim of this wor ...

Springer, Cham2022

NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs

Mirjana Stojilovic, Stefan Nikolic, Morten Borup Petersen

Novel applications have triggered significant changes at the system level of FPGA architecture design, such as the introduction of embedded VLIW processor arrays and hardened NoCs. However, the routing architecture of the soft logic fabric has largely rema ...

2021