Publications by Adam Shmuel Teman

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher pow ...

MDPI2024

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman, Robert Giterman

The rise of data-intensive applications has resulted in an increasing demand for high-density and low-power on-chip embedded memories. Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible alternative to conventional static random access memory (SRAM) w ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Gain-Cell Embedded DRAMs: Modeling and Design Space

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman, Robert Giterman

Among the different types of DRAMs, gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power and CMOS-compatible alternative to conventional SRAM. GC-eDRAM achieves high memory density as it relies on a storage cell that can be implemented with as few as ...

IEEE2020

A 1-Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16-nm FinFET

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman

Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible embedded memory alternative to SRAM, offering higher density, lower leakage power consumption, and an inherent two-ported functionality. However, increased leakage currents and process variations und ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman, Robert Giterman

Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to conventional SRAM due to its high-density, low-leakage, and inherent two-ported functionality. However, its dynamic storage mechanism requires power-hungry refresh cycles to maintain data. ...

IEEE2020

Gain-Cell Embedded DRAMs: Modeling and Design Space

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman, Robert Giterman

Among the different types of dynamic random-access memories (DRAMs), gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power, and CMOS-compatible alternative to conventional static random-access memory (SRAM). GC-eDRAM achieves high memory density, as i ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman, Robert Giterman

Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to conventional SRAM due to its high-density, low-leakage, and inherent two-ported functionality. However, its dynamic storage mechanism requires power-hungry refresh cycles to maintain data. ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection

Adam Shmuel Teman, Robert Giterman

A gain-cell embedded DRAM (GC-eDRAM) is an attractive logic-compatible alternative to the conventional static random access memory (SRAM) for the implementation of embedded memories, as it offers higher density, lower leakage, and two-ported operation. How ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI

Andreas Peter Burg, Jeremy Hugues-Felix Constantin, Andrea Bonetti, Adam Shmuel Teman

The increasing impact of variability on near-threshold nanometer circuits calls for a tighter online monitoring and control of the available timing margins. Error-detection sequentials are widely used together with error-correction techniques to operate di ...

IEEE2018

A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman

2018

A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Adam Shmuel Teman, Reza Ghanaatian Jahromi, Thomas Christoph Müller

2018

An 800-MHz Mixed-V-T 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman

2018

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster

Luca Benini, Andreas Peter Burg, Jeremy Hugues-Felix Constantin, Adam Shmuel Teman

This article presents an ultra-low-power parallel computing platform and its system-on-chip (SoC) embodiment, targeting a wide range of emerging near-sensor processing tasks for Internet of Things (IoT) applications. The proposed SoC achieves 193 million o ...

Institute of Electrical and Electronics Engineers2017

Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman

Reconfigurable finite-impulse response (FIR) filters are one of the most widely implemented components in Internet of Things systems that require flexibility to support several target applications while consuming the minimum amount of power to comply with ...

Ieee-Inst Electrical Electronics Engineers Inc2017

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes

Andreas Peter Burg, Nicholas Alexander Preyss, Andrea Bonetti, Adam Shmuel Teman

Clocking power, including both clock distribution and registers, has long been one of the primary factors in the total power consumption of many digital systems. One straightforward approach to reduce this power consumption is to apply dual-edge-triggered ...

Association for Computing Machinery2017

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Pascal Andreas Meinerzhagen, Luca Benini, Andreas Peter Burg, Adam Shmuel Teman

Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon area, power dissipation, and performance; however, static random access memories (SRAMs) are almost exclusively supplied by a small number of vendors throug ...

Association for Computing Machinery2016

Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman

Logic compatible gain cell (GC) embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, non-ratioed operation, low static leakage, and 2-port functionality. However, traditional GC-eDRAM implementations require boosted c ...

Ieee-Inst Electrical Electronics Engineers Inc2016

A Process Compensated Gain Cell Embedded-DRAM for Ultra-Low-Power Variation-Aware Design

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman

Gain cell embedded DRAM (GC-eDRAM) is a high-density alternative to SRAM for ultra-low-power systems. However, due to its dynamic nature, GC-eDRAM requires power-hungry refresh cycles to ensure data retention. Traditional design approaches dictate configur ...

Ieee2016

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Lorenz Flavio Schmid, Jeremy Hugues-Felix Constantin, Andrea Bonetti, Adam Shmuel Teman, Thomas Christoph Müller

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

A Low-Power Correlator for Wakeup Receivers with Algorithm Pruning through Early Termination

Andreas Peter Burg, Jeremy Hugues-Felix Constantin, Adam Shmuel Teman, Reza Ghanaatian Jahromi

A low-complexity, low-power digital correlator for wakeup receivers is presented. With the proposed algorithm, unnecessary computational cycles are dynamically pruned from the correlation using an early threshold check. For the algorithm, we provide a rigo ...

Ieee2016