Publication

SATSoT: A Methodology to Map Controllable-Polarity Devices on a Regular Fabric Using SAT

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Catherine Lucie Jéromine Gasnier
2013
Conference Papers

Abstract

Devices with controllable-polarity, such as Double-Gate Vertically-Stacked Nanowire FETs, have shown promising interests in recent years to implement XOR-based logic functions in an unprecedented compact way. Such a compactness is obtained at the cost of a denser interconnect, that can be mitigated by designing an efficient hyper-regular layout structure, called Sea-of-Tiles. In this paper, we propose a methodology, based on Boolean satisfiability, to map netlists of transistors on such a structure. The methodology endeavors to minimize the wiring complexity, by maximizing the sharing of the different terminals. We showed that its implementation, SATSoT, is able to automatically generate compact mappings with wiring complexities similar to manual layouts.

Official source

https://infoscience.epfl.ch/entities/publication/395c8e47-ae38-483c-8f5c-10dc12925b67

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Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Catherine Lucie Jéromine Gasnier
2013
Conference Papers

Abstract

Official source

https://infoscience.epfl.ch/entities/publication/395c8e47-ae38-483c-8f5c-10dc12925b67

About this result

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