SATSoT: A Methodology to Map Controllable-Polarity Devices on a Regular Fabric Using SAT

Devices with controllable-polarity, such as Double-Gate Vertically-Stacked Nanowire FETs, have shown promising interests in recent years to implement XOR-based logic functions in an unprecedented compact way. Such a compactness is obtained at the cost of a denser interconnect, that can be mitigated by designing an efficient hyper-regular layout structure, called Sea-of-Tiles. In this paper, we propose a methodology, based on Boolean satisfiability, to map netlists of transistors on such a structure. The methodology endeavors to minimize the wiring complexity, by maximizing the sharing of the different terminals. We showed that its implementation, SATSoT, is able to automatically generate compact mappings with wiring complexities similar to manual layouts.