Publications associées à Intel 4004

First developments towards producing inductive magnetic sensors using state-of-the-art photolithography techniques

Duccio Testa, Marcus Cemes, Ambrine Douhane

Inductive magnetic sensors are needed for tokamak operation to provide the low-frequency (LF) measurements leading to the equilibrium reconstruction and to monitor the higher frequency (HF) instabilities; the HF magnetic sensors are often also used as a ba ...

2023

Cooperative Concurrency Control for Write-Intensive Key-Value Workloads

Babak Falsafi, Alexandros Daglis, Mark Johnathon Sutherland

Key-Value Stores (KVS) are foundational infrastructure components for online services. Due to their latency-critical nature, today’s best-performing KVS contain a plethora of full-stack optimizations commonly targeting read-mostly, popularity-skewed worklo ...

ACM2023

Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse

This paper presents the set of simulation means used to develop the concept of N2C2 (neural network compute cube) based on a vertical transistor technology platform. On the basis of state-of-the-art junctionless nanowire transistors (JLNT), TCAD simulation ...

2021

Malware in the SGX supply chain: Be careful when signing enclaves!

Rafael Pereira Pires, Pascal Felber

Malware attacks are a significant part of the new software security threats detected each year. Intel Software Guard Extensions (SGX) are a set of hardware instructions introduced by Intel in their recent lines of processors that are intended to provide a ...

2022

Polynomial Evaluation on Superscalar Architecture, Applied to the Elementary Function e(x)

Felix Schürmann, Francesco Cremonesi, Timothée Ewart, Fabien Jonathan Delalondre

The evaluation of small degree polynomials is critical for the computation of elementary functions. It has been extensively studied and is well documented. In this article, we evaluate existing methods for polynomial evaluation on superscalar architecture. ...

2020

Massively parallel data processing for quantitative total flow imaging with optical coherence microscopy and tomography

Theo Lasser, Paul James Marchand, Daniel Pawel Szlag, Marcin Antoni Sylwestrzak

We present an application of massively parallel processing of quantitative flow measurements data acquired using spectral optical coherence microscopy (SOCM). The need for massive signal processing of these particular datasets has been a major hurdle for m ...

Elsevier2017

A reproducible method for μm precision alignment of PDMS microchannels with on-chip electrodes using a mask aligner

Philippe Renaud, Jonathan Bastien Cottet

This paper describes a reproducible method for μm precision alignment of polydimethylsiloxane (PDMS) microchannels with coplanar electrodes using a conventional mask aligner for lab-on-a-chip applications. It is based on the use of a silicon mold in combin ...

American Institute of Physics2017

Easy and Accurate Hardware-based Program Performance Monitoring

Andrzej Pawel Nowak

The performance monitoring of computer systems is a complex affair, made even more challenging by the increasing gap between hardware and software. Methods that collect and feed data to performance analysis can usually be classified into one of two groups. ...

EPFL2017

A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

Edoardo Charbon, Scott Anthony Lindner, Martin Wolf

We present a complete pixel based on a single-photon avalanche diode (SPAD) fabricated in a backside-illuminated (BSI) 3D IC technology. The chip stack comprises an image sensing tier produced in a 65-nm image sensor technology and a data processing tier i ...

Institute of Electrical and Electronics Engineers2017

A 65nm pixel readout ASIC with quick transverse momentum discrimination capabilities for the CMS Tracker at HL-LHC

Alessandro Caratelli, Davide Ceresa

A readout ASIC for the hybrid pixel detector with the capability of performing quick recognition of particles with high transverse momentum has been designed for the requirements of the CMS Outer Tracker at the High Luminosity LHC. The particle momentum di ...

Iop Publishing Ltd2016

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

Jeremy Hugues-Felix Constantin

With the omnipresence of embedded processing in all forms of electronics today, there is a strong trend towards wireless, battery-powered, portable embedded systems which have to operate under stringent energy constraints. Consequently, low power consumpti ...

EPFL2016

Hardware-Oriented Dynamically Adaptive Disparity Estimation Algorithm and its Real-Time Hardware

Alexandre Schmid, Yusuf Leblebici, Irem Boybat Kara, Abdulkadir Akin, Hüseyin Baris Atakan, Ipek Baz

A real-time stereo camera disparity estimation device comprises input means arranged to input measured data corresponding to rows of left and right images; a plurality of on-chip memories arranged to buffer the input measured data; a vertical rotator hardw ...

2015

Memory Systems and Interconnects for Scale-Out Servers

Stavros Volos

The information revolution of the last decade has been fueled by the digitization of almost all human activities through a wide range of Internet services. The backbone of this information age are scale-out datacenters that need to collect, store, and proc ...

EPFL2015

Modeling Minority Carriers Related Capacitive Effects for Transient Substrate Currents in Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

This paper presents an extended model for transient and ac circuit-level simulation of minority carriers propagation through the substrate of smart power integrated circuits (ICs). A p-n junction and a diffusion resistor with capacitive components are prop ...

Institute of Electrical and Electronics Engineers2015

Multi-Gigabyte On-Chip DRAM Caches for Servers

Dorde Jevdic

While DRAM latency has long been recognized as a major bottleneck in servers, DRAM bandwidth is emerging as an important bottleneck as server processors shift to many-core architectures to allow for sustainable throughput improvements. The rapid expansion ...

EPFL2015

A 15 mu W 5.5 kS/s Resistive Sensor Readout Circuit with 7.6 ENOB

Catherine Dehollain

A low power SAR logic-based resistive sensor readout circuit is proposed. A high sensitivity thermistor is used for local temperature measurements. The need for a low-noise front-end voltage amplifier is avoided by employing time-domain operation. In each ...

Institute of Electrical and Electronics Engineers2014

Cmos compatible non-volatile latch and d-flip flop using resistive switching materials

Davide Sacchetto, Yusuf Leblebici, Tugba Demirci

A non-volatile latch circuitry, comprising a Re RAM cell configured to store a final value of the non-volatile latch circuitry; a data selection circuitry configured to connect or disconnect a data input to a plus voltage node and a minus voltage node of t ...

2014

EigenMaps: Algorithms for Optimal Thermal Maps Extraction and Sensor Placement on Multicore Processors

Martin Vetterli, David Atienza Alonso, Juri Ranieri, Amina Chebira, Alessandro Vincenzi

Chip designers place on-chip sensors to measure local temperatures, thus preventing thermal runaway situations in multicore processing architectures. However, thermal characterization is directly dependent on the number of placed sensors, which should be m ...

ACM2012

3D Integration Technology for Lab-on-a-Chip Applications

Yüksel Temiz

This study adds a new dimension to lab-on-a-chip systems by employing three-dimensional (3D) integration technology for improved performance, higher functionality, and on-chip computational power. Despite the extensive amount of current research on 3D memo ...

EPFL2012

Current-Mode Analog Adaptive Mechanism for Ultralow-Power Neural Networks

Rafal Tomasz Dlugosz

Neural networks (NNs) implemented at the transistor level are powerful adaptive systems. They can perform hundreds of operations in parallel but at the expense of a large number of building blocks. In the case of analog realization, an extremely low chip a ...

Institute of Electrical and Electronics Engineers2011