Publications associées à Chronologie des microprocesseurs

A Compact Front-End Circuit for a Monolithic Sensor in a 65-nm CMOS Imaging Technology

This article presents the design of a front-end circuit for monolithic active pixel sensors (MAPSs). The circuit operates with a sensor featuring a small, low-capacitance (

Ieee-Inst Electrical Electronics Engineers Inc2023

Cascaded all-optical quantization employing step-size MMI and shape-optimized power splitter

Jijun He, Xiaowei Zhang, Jian Wu, Ye Tian

As a key unit of future high-throughput communications, optical analog to digital converter (OADC) with all-optical quantizer element that simultaneously possesses high resolution, large bandwidth and compact size is highly promising. A pending issue of co ...

ELSEVIER SCI LTD2023

Integrated electronics for time-of-flight positron emission tomography photodetectors

Andrada Alexandra Muntean

Positron emission tomography is a nuclear imaging technique well known for its use in oncology for cancer diagnosis and staging. A PET scanner is a complex machine which comprises photodetectors placed in a ring configuration that detect gamma photons gen ...

EPFL2023

A Low-noise CMOS SPAD Pixel with 12.1 ps SPTR and 3 ns Dead Time

Edoardo Charbon, Claudio Bruschini, Ming-Lo Wu, Francesco Gramuglia, Myung Jae Lee

In this paper, we present the first CMOS SPAD with performance comparable or better than that of the best custom SPADs, to date. The SPAD-based design, fully integrated in 180 nm CMOS technology, achieves a peak PDP of 55% at 480nm with a very broad spectr ...

2022

Nanowatt Acoustic Inference Sensing Exploiting Nonlinear Analog Feature Extraction

Christian Enz, Minhao Yang, Jun Zhang

Ultralow-power sensing with inference functionality embedded in sensor nodes is essential for enabling the emerging pervasive intelligence. For acoustic inference sensing, the feature extraction can take advantage of power-efficient analog circuits. Howeve ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Enhanced-performance integrated Resonant Switched-Capacitor and Buck DC-DC converters for application in extreme radiation and magnetic field environments

Giacomo Ripamonti

DC-DC converters based on Application Specific Integrated Circuits (ASICs) have been developed in this doctoral work for the High-Luminosity Large Hadron Collider (HL-LHC) experiments at CERN. They step down the voltage from a 2.5 V line and supply a load ...

EPFL2020

On-Chip Fully Integrated Field Emission Arrays for High-Voltage MEMS Applications

Vivek Subramanian

Vacuum-sealed fully integrated diode and triode field emission arrays based on Ti Spindt-type field emitters have been developed in a scalable, CMOS-compatible process directly on Si. Diode characterization in air demonstrates effective vacuum sealing and ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks

Giovanni De Micheli, Mathias Soeken, Luca Gaetano Amarù, Eleonora Testa, Heinz Riener

Logic synthesis is a fundamental step in the realization of modern integrated circuits. It has traditionally been employed for the optimization of CMOS-based designs, as well as for emerging technologies and quantum computing. Recently, it found applicatio ...

IEEE2020

Ionizing-Radiation Response and Low-Frequency Noise of 28-nm MOSFETs at Ultrahigh Doses

Christian Enz

Total ionizing dose (TID) mechanisms are investigated in 28-nm MOSFETs via dc static and low-frequency noise measurements. nMOSFETs and pMOSFETs are irradiated up to 1 Grad(SiO2) and annealed at high temperatures. TID sensitivity depends on the channel len ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Survey of Precision-Scalable Multiply-Accumulate Units for Neural-Network Processing

Christian Enz, Vincent Frédéric Camus

The current trend for deep learning has come with an enormous computational need for billions of Multiply-Accumulate (MAC) operations per inference. Fortunately, reduced precision has demonstrated large benefits with low impact on accuracy, paving the way ...

IEEE2019

Review and Benchmarking of Precision-Scalable Multiply-Accumulate Unit Architectures for Embedded Neural-Network Processing

Christian Enz, Vincent Frédéric Camus

The current trend for deep learning has come with an enormous computational need for billions of Multiply-Accumulate (MAC) operations per inference. Fortunately, reduced precision has demonstrated large benefits with low impact on accuracy, paving the way ...

2019

Performance improvement of chip-level CMOS-integrated ReRAM cells through material optimization

Elmira Shahrabi, Thomas La Grange, Yusuf Leblebici, Tugba Demirci

The integration of the resistive random access memory (ReRAM) with CMOS logic circuitry provides a solution to scaling limitations, and offers promising candidates for use in next generation computing applications. It is challenging to realize a reliable, ...

ELSEVIER SCIENCE BV2019

Modeling of Total Ionizing Dose Degradation on 180-nm n-MOSFETs Using BSIM3

Nergiz Sahin Solmaz, Mustafa Berke Yelten, Sadik Ilik

This paper presents a modeling approach to simulate the impact of total ionizing dose (TID) degradation on low-power analog and mixed-signal circuits. The modeling approach has been performed on 180-nm n-type metal-oxide-semiconductor field-effect transist ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Sweat Biomarker Sensor Incorporating Picowatt, Three-Dimensional Extended Metal Gate Ion Sensitive Field Effect Transistors

Mihai Adrian Ionescu, Junrui Zhang, Erick Antonio Garcia Cordero, Maneesha Rupakula, Hoël Maxime Guérin, Francesco Bellando, Fabien Patrick Wildhaber, Guillaume Charles Henri Herment

Ion sensitive field effect transistors (ISFETs) form a very attractive solution for wearable sensors due to their capacity for ultra-miniaturization, low power operation, and very high sensitivity, supported by complementary metal oxide semiconductor (CMOS ...

2019

ReRAM From Material Study to CMOS Co-integration

Elmira Shahrabi

The revolution of information-technology owes to silicon-based complementary-metal-oxide (CMOS) technology. However, CMOS technology approaches its physical limitation hardening the further progress of memory devices as well as computing paradigm requiring ...

EPFL2019

A back-illuminated 3D-stacked single-photon avalanche diode in 45nm CMOS technology

Edoardo Charbon, Myung Jae Lee, Preethi Padmanabhan, Augusto Ronchini Ximenes

We report on the world's first back-illuminated 3D-stacked single-photon avalanche diode (SPAD) in 45nm CMOS technology. This SPAD achieves a dark count rate of 55.4cps/μm 2 , a maximum photon detection probability of 31.8% at 600nm, over 5% in the 420-920 ...

2018

High-Performance Back-Illuminated Three-Dimensional Stacked Single-Photon Avalanche Diode Implemented in 45-nm CMOS Technology

Edoardo Charbon, Myung Jae Lee, Preethi Padmanabhan, Augusto Ronchini Ximenes

We present a high-performance back-illuminated three-dimensional stacked single-photon avalanche diode (SPAD), which is implemented in 45-nm CMOS technology for the first time. The SPAD is based on a P + /Deep N-well junction with a circular shape, for whi ...

2018

Time-resolved Single-photon Detector Arrays for High Resolution Near-infrared Optical Tomography

Scott Anthony Lindner

Oxygenation is an important marker in many clinical settings, e.g. diagnosing ischaemic brain injuries in preterm infants or determining treatment effectiveness in cancer patients. Despite significant efforts to determine the oxygenation state of the human ...

EPFL2018

Avalanche Microwave Noise Sources in Commercial 90-nm CMOS Technology

Christian Enz, Pierre-André Farine, Cyril Botteron, Gabriele Tasselli

This paper presents a microwave noise source implemented in a commercial CMOS technology. The circuit is based on the avalanche noise generated by both the source-to-bulk and the drain-to-bulk junctions in reverse breakdown. Two sources of different juncti ...

Institute of Electrical and Electronics Engineers2016

High-Voltage Tolerant Bi-State Self-Biasing Output Driver using Cascade Complementary Latches in Twin-well CMOS Technology

Scott Anthony Lindner

The design of a bi-state output buffer that can handle 5 times the supply voltage is presented. The use of self-biasing stacked devices driven by a cascade of complementary latches allows all devices to operate within the limits set by the technology, thus ...

Ieee2016