Publications associées à Table de hachage

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

Applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on FPGAs due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by re ...

ASSOC COMPUTING MACHINERY2022

Indexing Protected Deep Face Templates by Frequent Binary Patterns

Sébastien Marcel, Hatef Otroshi Shahreza

In this work, we present a simple biometric indexing scheme which is binning and retrieving cancelable deep face templates based on frequent binary patterns. The simplicity of the proposed approach makes it applicable to unprotected as well as protected, i ...

IEEE2022

Byzantine Consensus is Θ(n^2): The Dolev-Reischuk Bound is Tight even in Partial Synchrony!

Rachid Guerraoui, Jovan Komatovic, Vincent Gramoli, Pierre Philippe Civit, Seth Gilbert, Manuel José Ribeiro Vidigueira

The Dolev-Reischuk bound says that any deterministic Byzantine consensus protocol has (at least) quadratic communication complexity in the worst case. While it has been shown that the bound is tight in synchronous environments, it is still unknown whether ...

Dagstuhl Publishing2022

A Standalone FPGA-Based Miner for Lyra2REv2 Cryptocurrencies

Alexios Konstantinos Balatsoukas Stimming, Pascal Giard, Michiel Van Beirendonck

Lyra2REv2 is a hashing algorithm that consists of a chain of individual hashing algorithms, and it is used as a proof-of-work function in several cryptocurrencies. The most crucial and exotic hashing algorithm in the Lyra2REv2 chain is a specific instance ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Network coded multipath and related techniques

Emre Telatar, Arno Schneuwly, Derya Malak

Techniques are disclosed for adaptive coding and scheduling of packets in wireless networks. The adaptive coding and scheduling can be achieved by utilizing a discrete water filling (DWF) scheme. In an example, a computer-implemented method to adaptively c ...

2020

Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs

Paolo Ienne, Mikhail Asiatici

FPGAs rely on massive datapath parallelism to accelerate applications even with a low clock frequency. However, applications such as sparse linear algebra and graph analytics have their throughput limited by irregular accesses to external memory for which ...

ASSOC COMPUTING MACHINERY2019

A Lyra2 FPGA Core for Lyra2REv2-Based Cryptocurrencies

Alexios Konstantinos Balatsoukas Stimming, Pascal Giard, Michiel Van Beirendonck

Lyra2REv2 is a hashing algorithm that consists of a chain of individual hashing algorithms and it is used as a proof-of-work function in several cryptocurrencies that aim to be ASIC-resistant. The most crucial hashing algorithm in the Lyra2REv2 chain is a ...

IEEE2019

Closing the Performance Gap Between Volatile and Persistent Key-Value Stores Using Cross-Referencing Logs

Matej Pavlovic

Key-Value (K-V) stores are an integral building block in modern datacenter applications. With byteaddressable persistent memory (PM) technologies, such as Intel/Micron's 3D XPoint, on the horizon, there has been an influx of new high performance K-V stores ...

USENIX ASSOC2018

Log-Free Concurrent Data Structures

Rachid Guerraoui, Aleksandar Dragojevic, Mihail Igor Zablotchi, Tudor Alexandru David

Non-volatile RAM (NVRAM) makes it possible for data structures to tolerate transient failures, assuming however that programmers have designed these structures such that their consistency is preserved upon recovery. Previous ap- proaches are typically tran ...

USENIX Association2018

Log-Free Concurrent Data Structures

Rachid Guerraoui, Aleksandar Dragojevic, Mihail Igor Zablotchi, Tudor Alexandru David

Non-volatile RAM (NVRAM) makes it possible for data structures to tolerate transient failures, assuming however that programmers have designed these structures such that their consistency is preserved upon recovery. Previous approaches are typically transa ...

USENIX ASSOC2018

A Blockchain Consensus Protocol With Horizontal Scalability

Kelong Cong

Blockchain technology has the potential to decentralise many traditionally centralised systems. However, scalability remains a key challenge. A horizontally scalable solution, where performance increases by adding more nodes, would move blockchain systems ...

IEEE2018

Elastic transactions

Rachid Guerraoui, Vincent Gramoli, Pascal Felber

This paper presents elastic transactions, an appealing alternative to traditional transactions, in particular to implement search structures in shared memory multicore architectures. Upon conflict detection, an elastic transaction might drop what it did so ...

Academic Press Inc Elsevier Science2017

Efficient Logging in Non-Volatile Memory by Exploiting Coherency Protocols

James Richard Larus, Nachshon Cohen

Non-volatile memory (NVM) technologies such as PCM, ReRAM and STT-RAM allow processors to directly write values to persistent storage at speeds that are significantly faster than previous durable media such as hard drives or SSDs. Many applications of NVM ...

ACM2017

Rake, Peel, Sketch : The Signal Processing Pipeline Revisited

Robin Scheibler

The prototypical signal processing pipeline can be divided into four blocks. Representation of the signal in a basis suitable for processing. Enhancement of the meaningful part of the signal and noise reduction. Estimation of important statistical properti ...

EPFL2017

Optimistic Concurrency with OPTIK

Rachid Guerraoui, Vasileios Trigonakis

We introduce OPTIK, a new practical design pattern for designing and implementing fast and scalable concurrent data structures. OPTIK relies on the commonly-used technique of version numbers for detecting conflicting concurrent operations. We show how to i ...

ACM Press2016

Towards Scalable Synchronization on Multi-Cores

Vasileios Trigonakis

The shift of commodity hardware from single- to multi-core processors in the early 2000s compelled software developers to take advantage of the available parallelism of multi-cores. Unfortunately, only few---so-called embarrassingly parallel---applications ...

EPFL2016

Method for determining the walsh-hadamard transform of n samples of a signal and apparatus for performing the same

Martin Vetterli, Robin Scheibler, Saeid Haghighatshoar

A computer-implemented method for determining the Walsh-Hadamard transform of N samples of a signal, comprises electing a plurality of hashing C matrices Σ1, . . . ΣC, computing C hashes of a particular length based at least on a hashing front end and the ...

2015

Asynchronous memory access chaining

Babak Falsafi, Boris Robert Grot, Yusuf Onur Koçberber

In-memory databases rely on pointer-intensive data structures to quickly locate data in memory. A single lookup operation in such data structures often exhibits long-latency memory stalls due to dependent pointer dereferences. Hiding the memory latency by ...

2015

Enhanced Compressed Look-up-Table Based Real-Time Rectification Hardware

Alexandre Schmid, Yusuf Leblebici, Abdulkadir Akin, Halima Najibi, Luis Manuel Gaemperle

Real-time disparity estimation requires real-time rectification which involves solving the models of lens distortions, image translations and rotations. Low complexity look-up-table based rectification algorithms usually require an external memory to store ...

Springer-Verlag Berlin2015

Online indexing and distributed querying model-view sensor data in the cloud

Karl Aberer, Tian Guo, Hao Zhuang

As various kinds of sensors penetrate our daily life (e.g., sensor networks for environmental monitoring, GPS for localization and navigation), the efficient management of massive amount of sensor data becomes increasingly important at present. Many sensor ...

Springer-Verlag Berlin2014