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Publications associées (30)

A 6.5-GHz Cryogenic All-Pass Filter Circulator in 40-nm CMOS for Quantum Computing Applications

Edoardo Charbon, Andrea Ruffino, Yatao Peng, Fabio Sebastiano

Cryogenic solid-state quantum processors require classical control and readout electronics; to achieve compactness and scalability, cryogenic integrated circuits have been recently proposed for this goal. Circulators are widely used in readout circuits, ho ...

2019

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Edoardo Charbon, Fabio Sebastiano

Cryogenic device models are essential for the reliable design of the cryo-CMOS interface that enables large-scale quantum computers. In this paper, mismatch characterization and modeling of a 40-nm bulk CMOS process over the 4.2-300 K temperature range is ...

IEEE2019

Fabrication and Characterization of Freestanding Single Crystal Diamond and Silicon Microresonators

Teodoro Graziosi

Microresonators are fundamental building blocks of any photonic integrated circuit, as they can be used as filters, modulators, sensors, and to enhance light emission. If these resonators are suspended and are free to oscillate, we can exploit the interact ...

EPFL2019

An Eight lanes 7Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels

Volkan Cevher, Cosimo Aprile, Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Thomas Toifl

This paper presents a versatile crosstalk cancellation scheme for single-ended multi-lane backplane links. System-level investigations show that a scheme, which combines analog filters and decision-feedback crosstalk compensation on the receiver (RX) side ...

2018

Trading off Energy versus Accuracy in Modern Computing Systems : From Digital Circuit Design to Programming Techniques

Jérémy Lucien Maurice Schlachter

The slowdown of Moore's law, which has been the driving force of the electronics industry over the last 5 decades, is causing serious problem to Integrated Circuits (ICs) improvements. Technology scaling is becoming more and more complex and fabrication co ...

EPFL2018

Integrated Bio/Nano/CMOS Interfaces for Electrochemical Molecular Sensing

Sandro Carrara

Integrated bio/nano/Complementary Metal-Oxide-Semiconductor (CMOS) interfaces for electrochemical molecular sensing are becoming more and more common in the literature, especially for developing new electronic biochips for smart and intelligent Internet-of ...

WILEY2018

Benchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic Analog Functions

Mihai Adrian Ionescu, Cem Alper, Arnab Biswas, Florin Udrea

This paper reports a compact ambipolar model for homojunction strained-silicon (sSi) nanowire (NW) tunnel FETs (TFETs) capable of accurately describing both I-V and G-V characteristics in all regimes of operation, n- and p-ambipolarity, the superlinear ons ...

Institute of Electrical and Electronics Engineers2017

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies

Yusuf Leblebici

Thermal behaviours of high-performance digital circuits in bulk CMOS and FDSOI technologies are compared on a 64-bit Kogge-Stone adder designed in 40nm CMOS node. Temperature profiles of the adder in bulk and FDSOI are extracted with thermal simulations an ...

Elsevier Science Bv2017

Three-Dimensional Nano-Acoustic Bragg Reflectors for CMOS Embedded NEMS

Luis Guillermo Villanueva Torrijo, Soumya Yandrapalli, David Ruffieux

Integration of CMOS electronic circuits and electromechanical resonators has been pursued for a long time by many different research groups and even foundries. This would improve the overall performance of electromechanical oscillators and sensors. However ...

Institute of Electrical and Electronics Engineers2017

A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

Edoardo Charbon, Scott Anthony Lindner, Martin Wolf

We present a complete pixel based on a single-photon avalanche diode (SPAD) fabricated in a backside-illuminated (BSI) 3D IC technology. The chip stack comprises an image sensing tier produced in a 65-nm image sensor technology and a data processing tier i ...

Institute of Electrical and Electronics Engineers2017

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