Publications associées à VideoCore

Impact of Video Processing Operations in Deepfake Detection

The detection of digital face manipulation in video has attracted extensive attention due to the increased risk to public trust. To counteract the malicious usage of such techniques, deep learning-based deepfake detection methods have been developed and ha ...

2023

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

Gem5-X : A Many-Core Heterogeneous Simulation Platform for Architectural Exploration and Optimization

David Atienza Alonso, Marina Zapater Sancho, William Andrew Simon, Yasir Mahmood Qureshi

The increasing adoption of smart systems in our daily life has led to the development of new applications with varying performance and energy constraints, and suitable computing architectures need to be developed for these new applications. In this paper, ...

2021

Micro-architectural Analysis of OLAP: Limitations and Opportunities

Anastasia Ailamaki, Utku Sirin

Understanding micro-architectural behavior is important for efficiently using hardware resources. Recent work has shown that in-memory online transaction processing (OLTP) systems severely underutilize their core micro-architecture resources [29]. Whereas, ...

ASSOC COMPUTING MACHINERY2020

Lenstool-HPC: A High Performance Computing based mass modelling tool for cluster-scale gravitational lenses

Jean-Paul Richard Kneib, Christoph Ernst René Schäfer

With the upcoming generation of telescopes, cluster scale strong gravitational lenses will act as an increasingly relevant probe of cosmology and dark matter. The better resolved data produced by current and future facilities requires faster and more effic ...

ELSEVIER2020

Asynchronous Branch-Paralle Simulation of Detailed Neuron Models

Felix Schürmann, Michael Lee Hines

Simulations of electrical activity of networks of morphologically detailed neuron models allow for a better understanding of the brain. State-of-the-art simulations describe the dynamics of ionic currents and biochemical processes within branching topologi ...

2019

GPU Acceleration for Simulating Massively Parallel Many-Core Platforms

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

Emerging massively parallel architectures such as a general-purpose processor plus many-core programmable accelerators are creating an increasing demand for novel methods to perform their architectural simulation. Most state-of-the-art simulation technolog ...

Institute of Electrical and Electronics Engineers2015

Scalable Simulation Methodologies for Many-Core Heterogeneous Systems

Shivani Raghav

With increasing complexity and performance demands of emerging compute-intensive data-parallel workloads, many-core computing systems are becoming a popular trend in computer design. Fast and scalable simulation methods are needed to make meaningful predic ...

EPFL2014

Markov Decision Process Based Energy-Efficient Scheduling For Slice-Parallel Video Decoding

David Atienza Alonso, Karim Kanoun

We consider the problem of energy-efficient scheduling for slice-parallel video decoders on multicore systems with Dynamic Voltage Frequency Scaling (DVFS) enabled processors. We rigorously formulate the problem as a Markov decision process (MDP), which si ...

IEEE Press2013

Markov Decision Process Based Energy-Efficient On-Line Scheduling for Slice Parallel Video Decoders on Multicore Systems

Pascal Frossard, David Atienza Alonso, Karim Kanoun

We consider the problem of energy-efficient on-line scheduling for slice-parallel video decoders on multicore systems. We assume that each of the processors are Dynamic Voltage Frequency Scaling (DVFS) enabled such that they can independently trade off per ...

Ieee-Inst Electrical Electronics Engineers Inc2013

Methodology and Technique to Improve Throughput of FPGA-based CAL Dataflow Programs: Case Study of the RVC MPEG-4 SP Intra Decoder

Marco Mattavelli, Christophe Lucarz, Ihab Mostafa Amin Mohamed Amer, Ab Al Hadi Bin Ab Rahman, Hossam Amer

The specification of complex signal processing systems in hardware by means of HDL is no longer the appropriate way since they are known to be time consuming to design, and less flexible to extend features. Recently, \CAL dataflow language was specified to ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011